2008 | ||
---|---|---|
46 | EE | Thomas W. Williams: EDA to the Rescue of the Silicon Roadmap. ISMVL 2008: 1 |
45 | EE | Rohit Kapur, Subhasish Mitra, Thomas W. Williams: Historical Perspective on Scan Compression. IEEE Design & Test of Computers 25(2): 114-120 (2008) |
2007 | ||
44 | Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams: Accurately Determining Bridging Defects from Layout. DDECS 2007: 87-90 | |
43 | EE | Thomas W. Williams: EDA to the Rescue of the Silicon Roadmap. ISQED 2007: 115-118 |
42 | EE | Peter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini: Minimizing the Impact of Scan Compression. VTS 2007: 67-74 |
2005 | ||
41 | EE | Thomas W. Williams: Design for Testability: The Path to Deep Submicron. Asian Test Symposium 2005 |
40 | EE | Thomas W. Williams: TTTC recognizes test visionary's lifetime contribution. IEEE Design & Test of Computers 22(3): 282, 285 (2005) |
2004 | ||
39 | EE | Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams: Changing the Scan Enable during Shift. VTS 2004: 73-78 |
2003 | ||
38 | EE | Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch: Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. DATE 2003: 10110-10115 |
37 | EE | Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir: Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC 2003: 1041-1050 |
36 | EE | Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams: A Reconfigurable Shared Scan-in Architecture. VTS 2003: 9-14 |
2002 | ||
35 | EE | Rohit Kapur, Thomas W. Williams: Manufacturing Test of SoCs. Asian Test Symposium 2002: 317-319 |
34 | EE | Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374 |
33 | EE | Rohit Kapur, Thomas W. Williams, M. Ray Mercer: Directed-Binary Search in Logic BIST Diagnostics. DATE 2002: 1121 |
32 | EE | Nahmsuk Oh, Rohit Kapur, Thomas W. Williams: Fast seed computation for reseeding shift register in test pattern compression. ICCAD 2002: 76-81 |
31 | EE | Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416 |
30 | EE | Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams: Dynamic Scan: Driving Down the Cost of Test. IEEE Computer 35(10): 63-68 (2002) |
2001 | ||
29 | Peter Wohl, John A. Waicukauski, Thomas W. Williams: Design of compactors for signature-analyzers in built-in self-test. ITC 2001: 54-63 | |
28 | Rohit Kapur, Thomas W. Williams: Tester retargetable patterns. ITC 2001: 721-727 | |
27 | Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir: A new methodology for improved tester utilization. ITC 2001: 916-923 | |
26 | EE | Rohit Kapur, R. Chandramouli, Thomas W. Williams: Strategies for Low-Cost Test. IEEE Design & Test of Computers 18(6): 47-54 (2001) |
2000 | ||
25 | EE | F. Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu: DFT closure. Asian Test Symposium 2000: 8-9 |
24 | EE | Thomas W. Williams, Rohit Kapur: Design for Testability in Nanometer Technologies; Searching for Quality. ISQED 2000: 167-172 |
23 | EE | Rohit Kapur, Cy Hay, Thomas W. Williams: The Mutating Metric for Benchmarking Test. IEEE Design & Test of Computers 17(3): 18-21 (2000) |
22 | EE | Don MacMillen, Raul Camposano, Dwight D. Hill, Thomas W. Williams: An industrial view of electronic design automation. IEEE Trans. on CAD of Integrated Circuits and Systems 19(12): 1428-1448 (2000) |
1999 | ||
21 | Rohit Kapur, Thomas W. Williams: Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. IEEE Computer 32(11): 42-45 (1999) | |
1996 | ||
20 | EE | Li-C. Wang, M. Ray Mercer, Thomas W. Williams: A Better ATPG Algorithm and Its Design Principles. ICCD 1996: 248-253 |
19 | Li-C. Wang, M. Ray Mercer, Thomas W. Williams: Using Target Faults To Detect Non-Tartget Defects. ITC 1996: 629-638 | |
18 | Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly: IDDQ Test: Sensitivity Analysis of Scaling. ITC 1996: 786-792 | |
17 | EE | José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams: Defect level evaluation in an IC design environment. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1286-1293 (1996) |
16 | EE | Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams: A weighted random pattern test generation system. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 1020-1025 (1996) |
1995 | ||
15 | Li-C. Wang, M. Ray Mercer, Thomas W. Williams: On Efficiently and Reliably Achieving Low Defective Part Levels. ITC 1995: 616-625 | |
14 | EE | Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams: On the decline of testing efficiency as fault coverage approaches 100%. VTS 1995: 74-83 |
1994 | ||
13 | José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams: Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC 1994: 436-442 | |
12 | Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams: Design of an Efficient Weighted-Random-Pattern Generation System. ITC 1994: 491-500 | |
1993 | ||
11 | Thomas W. Williams: Design for Testability: Today and in the Future. ICCD 1993: 14 | |
1992 | ||
10 | Eun Sei Park, M. Ray Mercer, Thomas W. Williams: The Total Delay Fault Model and Statistical Delay Fault Coverage. IEEE Trans. Computers 41(6): 688-698 (1992) | |
1991 | ||
9 | EE | Thomas W. Williams, Bill Underwood, M. Ray Mercer: The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. DAC 1991: 87-92 |
8 | Kenneth D. Wagner, Thomas W. Williams: Enhancing Board Functional Self-Test by Concurrent Sampling. ITC 1991: 633-640 | |
7 | Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer: Delay Testing Quality in Timing-Optimized Designs. ITC 1991: 897-905 | |
1989 | ||
6 | Thomas W. Williams: Future Trends in the Testing. IFIP Congress 1989: 1019-1020 | |
1988 | ||
5 | Eun Sei Park, Thomas W. Williams, M. Ray Mercer: Statistical Delay Fault Coverage and Defect Level for Delay Faults. ITC 1988: 492-499 | |
4 | Kenneth D. Wagner, Thomas W. Williams: Design for Testability of Mixed Signal Integrated Circuits. ITC 1988: 823-828 | |
1984 | ||
3 | Thomas W. Williams: VLSI Testing. IEEE Computer 17(10): 126-136 (1984) | |
1982 | ||
2 | Eugen I. Muehldorf, Thomas W. Williams: Analysis of the Switching Behavior of Combinatorial Logic Networks. ITC 1982: 379-390 | |
1 | Thomas W. Williams, Kenneth P. Parker: Design for Testability - A Survey. IEEE Trans. Computers 31(1): 2-15 (1982) |