| 2007 |
|---|
| 31 | EE | Sezer Gören,
F. Joel Ferguson:
On state reduction of incompletely specified finite state machines.
Computers & Electrical Engineering 33(1): 58-69 (2007) |
| 2006 |
|---|
| 30 | EE | Sezer Gören,
F. Joel Ferguson:
Test sequence generation for controller verification and test with high coverage.
ACM Trans. Design Autom. Electr. Syst. 11(4): 916-938 (2006) |
| 2005 |
|---|
| 29 | EE | Shalini Ghosh,
F. Joel Ferguson:
Detection probabilities of interconnect breaks: an analysis.
Integration 38(3): 451-465 (2005) |
| 2004 |
|---|
| 28 | EE | Shalini Ghosh,
F. Joel Ferguson:
Estimating detection probability of interconnect opens using stuck-at tests.
ACM Great Lakes Symposium on VLSI 2004: 254-259 |
| 2002 |
|---|
| 27 | EE | Sezer Gören,
F. Joel Ferguson:
CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines.
DATE 2002: 248-254 |
| 26 | EE | Sezer Gören,
F. Joel Ferguson:
Testing Finite State Machines Based on a Structural Coverage Metric .
ITC 2002: 773-780 |
| 1999 |
|---|
| 25 | | Sezer Gören,
F. Joel Ferguson:
Checking sequence generation for asynchronous sequential elements.
ITC 1999: 406-413 |
| 24 | EE | Jingjing Xu,
Rahul Kundu,
F. Joel Ferguson:
A Systematic DFT Procedure for Library Cells.
VTS 1999: 460-466 |
| 23 | EE | Michael A. Margolese,
F. Joel Ferguson:
Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test.
VTS 1999: 80-85 |
| 1998 |
|---|
| 22 | EE | Jayashree Saxena,
Kenneth M. Butler,
Hari Balachandran,
David B. Lavo,
Tracy Larrabee,
F. Joel Ferguson,
Brian Chess:
On applying non-classical defect models to automated diagnosis.
ITC 1998: 748-757 |
| 21 | EE | Douglas Williams,
F. Joel Ferguson,
Tracy Larrabee:
A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric.
VTS 1998: 274-282 |
| 20 | EE | Haluk Konuk,
F. Joel Ferguson:
Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1200-1210 (1998) |
| 19 | EE | David B. Lavo,
Brian Chess,
Tracy Larrabee,
F. Joel Ferguson:
Diagnosing realistic bridging faults with single stuck-at information.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 255-268 (1998) |
| 1997 |
|---|
| 18 | | Haluk Konuk,
F. Joel Ferguson:
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits.
ITC 1997: 597-606 |
| 17 | | Richard McGowen,
F. Joel Ferguson:
Incorporating Physical Design-for-Test into Routing.
ITC 1997: 685-693 |
| 16 | | David B. Lavo,
Tracy Larrabee,
F. Joel Ferguson,
Brian Chess,
Jayashree Saxena,
Kenneth M. Butler:
Bridging Fault Diagnosis in the Absence of Physical Information.
ITC 1997: 887-893 |
| 15 | EE | A. Jee,
F. Joel Ferguson:
A methodolgy for characterizing cell testability.
VTS 1997: 384-390 |
| 1996 |
|---|
| 14 | EE | Haluk Konuk,
F. Joel Ferguson:
An unexpected factor in testing for CMOS opens: the die surface.
VTS 1996: 422-429 |
| 13 | | Martine D. F. Schlag,
F. Joel Ferguson:
Detection of Multiple Faults in Two-Dimensional ILAs.
IEEE Trans. Computers 45(6): 741-746 (1996) |
| 12 | EE | Haluk Konuk,
F. Joel Ferguson,
Tracy Larrabee:
Charge-based fault simulation for CMOS network breaks.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1555-1567 (1996) |
| 1995 |
|---|
| 11 | EE | Haluk Konuk,
F. Joel Ferguson,
Tracy Larrabee:
Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks.
DAC 1995: 345-351 |
| 10 | EE | Brian Chess,
David B. Lavo,
F. Joel Ferguson,
Tracy Larrabee:
Diagnosis of realistic bridging faults with single stuck-at information.
ICCAD 1995: 185-192 |
| 1994 |
|---|
| 9 | | Richard McGowen,
F. Joel Ferguson:
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT.
EDAC-ETC-EUROASIC 1994: 371-375 |
| 8 | | Brian Chess,
Anthony Freitas,
F. Joel Ferguson,
Tracy Larrabee:
Testing CMOS Logic Gates for Realistic Shorts.
ITC 1994: 395-402 |
| 7 | | Charles F. Hawkins,
Jerry M. Soden,
Alan W. Righter,
F. Joel Ferguson:
Defect Classes - An Overdue Paradigm for CMOS IC.
ITC 1994: 413-425 |
| 1991 |
|---|
| 6 | | F. Joel Ferguson,
Tracy Larrabee:
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs.
ITC 1991: 492-499 |
| 1990 |
|---|
| 5 | EE | F. Joel Ferguson:
Detection of multiple faults in MOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 1009-1014 (1990) |
| 1988 |
|---|
| 4 | | John Paul Shen,
F. Joel Ferguson:
Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis.
ITC 1988: 475-484 |
| 3 | EE | F. Joel Ferguson,
John Paul Shen:
A CMOS fault extractor for inductive fault analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(11): 1181-1194 (1988) |
| 1984 |
|---|
| 2 | | Wojciech Maly,
F. Joel Ferguson,
John Paul Shen:
Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells.
ITC 1984: 390-399 |
| 1 | | John Paul Shen,
F. Joel Ferguson:
The Design of Easily Tastabel VLSI Array Multipliers.
IEEE Trans. Computers 33(6): 554-560 (1984) |
