| 2008 |
|---|
| 32 | EE | Héctor Pettenghi,
Maria J. Avedillo,
José M. Quintana:
A novel contribution to the RTD-based threshold logic family.
ISCAS 2008: 2350-2353 |
| 31 | EE | Juan Núñez,
José M. Quintana,
Maria J. Avedillo:
Limits to a correct operation in RTD-based ternary inverters.
ISCAS 2008: 604-607 |
| 2007 |
|---|
| 30 | EE | Juan Núñez,
José M. Quintana,
Maria J. Avedillo:
Operation limits in RTD-based ternary quantizers.
ACM Great Lakes Symposium on VLSI 2007: 114-119 |
| 29 | EE | Héctor Pettenghi,
Maria J. Avedillo,
José M. Quintana:
Non Return Mobile Logic Family.
ISCAS 2007: 125-128 |
| 28 | EE | Juan Núñez,
José M. Quintana,
Maria J. Avedillo:
Limits to a Correct Evaluation in RTD-Based Quaternary Inverters.
ISMVL 2007: 51 |
| 27 | EE | Juan Núñez,
José M. Quintana,
Maria J. Avedillo:
A quasi-differential quantizer based on SMOBILE.
SBCCI 2007: 251-256 |
| 2006 |
|---|
| 26 | EE | José M. Quintana,
Maria J. Avedillo,
Juan Núñez:
Design Guides for a Correct DC Operation in RTD-based Threshold Gates.
DSD 2006: 530-536 |
| 25 | EE | José M. Quintana,
Maria J. Avedillo,
Héctor Pettenghi:
Self-latching operation limits for MOBILE circuits.
ISCAS 2006 |
| 2005 |
|---|
| 24 | EE | Maria J. Avedillo,
José M. Quintana,
Héctor Pettenghi:
Logic Models Supporting the Design of MOBILE-based RTD Circuits.
ASAP 2005: 254-259 |
| 23 | EE | Maria J. Avedillo,
José M. Quintana,
José L. Huertas:
Robust frequency divider based on resonant tunneling devices.
ISCAS (3) 2005: 2647-2650 |
| 2004 |
|---|
| 22 | EE | Maria J. Avedillo,
José M. Quintana:
A Threshold Logic Synthesis Tool for RTD Circuits.
DSD 2004: 624-627 |
| 21 | | José M. Quintana,
Maria J. Avedillo,
Héctor Pettenghi:
Programmable logic gate based on resonant tunnelling devices.
ISCAS (3) 2004: 697-700 |
| 20 | EE | Maria J. Avedillo,
José M. Quintana,
Raúl Jiménez-Naharro:
Pass-transistor based implementations of threshold logic gates for WOS filtering.
Microelectronics Journal 35(11): 869-873 (2004) |
| 19 | EE | Maria J. Avedillo,
José M. Quintana,
Hamid El Alami,
Antonio Jiménez-Calderón:
A Practical Parallel Architecture for Stacks Filters.
VLSI Signal Processing 38(2): 91-100 (2004) |
| 2003 |
|---|
| 18 | EE | Valeriu Beiu,
Maria J. Avedillo,
José M. Quintana:
Review of Capacitive Threshold Gate Implementations.
ICANN 2003: 737-744 |
| 17 | | Valeriu Beiu,
José M. Quintana,
Maria J. Avedillo:
Review of Differential Threshold Gate Implementations.
Neural Networks and Computational Intelligence 2003: 44-49 |
| 2002 |
|---|
| 16 | EE | Manuel Martínez,
Maria J. Avedillo,
José M. Quintana,
H. Süß,
Manfred Koegst:
An Encoding Technique for Low Power CMOS Implementations of Controllers.
DATE 2002: 1083 |
| 15 | EE | José M. Quintana,
Maria J. Avedillo,
José L. Huertas:
Simplified Reed-Muller expressions for residue threshold functions.
ISCAS (4) 2002: 599-602 |
| 14 | EE | Maria J. Avedillo,
José M. Quintana,
Esther Rodríguez-Villegas:
Simple parallel weighted order statistic filter implementations.
ISCAS (4) 2002: 607-610 |
| 13 | EE | Esther Rodríguez-Villegas,
José M. Quintana,
Maria J. Avedillo,
Adoración Rueda:
High-speed low-power logic gates using floating gates.
ISCAS (5) 2002: 389-392 |
| 2001 |
|---|
| 12 | EE | José M. Quintana,
Maria J. Avedillo,
Raúl Jiménez,
Esther Rodríguez-Villegas:
Practical low-cost CPL implementations threshold logic functions.
ACM Great Lakes Symposium on VLSI 2001: 139-144 |
| 11 | EE | José M. Quintana,
Maria J. Avedillo:
Reed-Muller descriptions of symmetric functions.
ISCAS (4) 2001: 682-685 |
| 10 | EE | José M. Quintana,
Maria J. Avedillo,
José Luis Huertas:
Efficient Realization of a Threshold Voter for Self-Purging Redundancy.
J. Electronic Testing 17(1): 69-73 (2001) |
| 1999 |
|---|
| 9 | EE | Manuel Martínez,
Maria J. Avedillo,
José M. Quintana,
José L. Huertas:
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length.
DATE 1999: 521-525 |
| 8 | EE | Esther Rodríguez-Villegas,
Maria J. Avedillo,
José M. Quintana,
Gloria Huertas,
Adoración Rueda:
vMOS-based sorters for multiplier implementations.
ISCAS (1) 1999: 338-341 |
| 1998 |
|---|
| 7 | EE | Manuel Martínez,
Maria J. Avedillo,
José M. Quintana,
José L. Huertas:
A Dynamic Model for the State Assignment Problem.
DATE 1998: 835-839 |
| 1997 |
|---|
| 6 | EE | Juan A. Prieto,
Adoración Rueda,
José M. Quintana,
José Luis Huertas:
A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs.
ED&TC 1997: 389-394 |
| 1995 |
|---|
| 5 | EE | José M. Quintana,
Maria J. Avedillo,
Maria P. Parra,
José L. Huertas:
Optimum PLA folding through boolean satisfiability.
ASP-DAC 1995 |
| 4 | EE | Maria J. Avedillo,
José M. Quintana,
José Luis Huertas:
Constrained state assignment of easily testable FSMs.
J. Electronic Testing 6(1): 133-138 (1995) |
| 1994 |
|---|
| 3 | | Juan A. Prieto,
José M. Quintana,
Adoración Rueda,
José L. Huertas:
An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits.
ISCAS 1994: 491-494 |
| 1993 |
|---|
| 2 | | Maria J. Avedillo,
José M. Quintana,
José L. Huertas:
Easily Testable PLA-based FSMS.
ISCAS 1993: 1603-1606 |
| 1990 |
|---|
| 1 | EE | Maria J. Avedillo,
José M. Quintana,
José Luis Huertas:
A new method for the state reduction of incompletely specified finite sequential machines.
EURO-DAC 1990: 552-556 |
