2009 |
41 | EE | Jungsoo Kim,
Seungyong Oh,
Sungjoo Yoo,
Chong-Min Kyung:
An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 568-581 (2009) |
2008 |
40 | EE | Soo-Kwan Eo,
Sungjoo Yoo,
Kyu-Myung Choi:
An industrial perspective of power-aware reliable SoC design.
ASP-DAC 2008: 555-557 |
39 | EE | Minje Jun,
Sungjoo Yoo,
Eui-Young Chung:
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches.
ASP-DAC 2008: 583-588 |
38 | EE | Woo-Cheol Kwon,
Sungjoo Yoo,
Sung-Min Hong,
Byeong Min,
Kyu-Myung Choi,
Soo-Kwan Eo:
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories.
DAC 2008: 447-452 |
37 | EE | Woo-Cheol Kwon,
Sung-Min Hong,
Sungjoo Yoo,
Byeong Min,
Kyu-Myung Choi,
Soo-Kwan Eo:
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication.
DATE 2008: 1244-1249 |
36 | EE | Sungpack Hong,
Sungjoo Yoo,
Byeong Bin,
Kyu-Myung Choi,
Soo-Kwan Eo,
Taehwan Kim:
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution.
DATE 2008: 242-247 |
35 | EE | Dongwook Lee,
Sungjoo Yoo,
Kiyoung Choi:
Entry control in network-on-chip for memory power reduction.
ISLPED 2008: 171-176 |
2007 |
34 | EE | Jun-hee Yoo,
Dongwook Lee,
Sungjoo Yoo,
Kiyoung Choi:
Communication Architecture Synthesis of Cascaded Bus Matrix.
ASP-DAC 2007: 171-177 |
2006 |
33 | EE | Ikhwan Lee,
Hyunsuk Kim,
Peng Yang,
Sungjoo Yoo,
Eui-Young Chung,
Kyu-Myung Choi,
Jeong-Taek Kong,
Soo-Kwan Eo:
PowerViP: Soc power estimation framework at transaction level.
ASP-DAC 2006: 551-558 |
32 | EE | Sungpack Hong,
Sungjoo Yoo,
Sheayun Lee,
Sangwoo Lee,
Hye Jeong Nam,
Bum-Seok Yoo,
Jaehyung Hwang,
Donghyun Song,
Janghwan Kim,
Jeongeun Kim,
HoonSang Jin,
Kyu-Myung Choi,
Jeong-Taek Kong,
Soo-Kwan Eo:
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study.
CODES+ISSS 2006: 235-240 |
31 | EE | Sungpack Hong,
Sungjoo Yoo,
HoonSang Jin,
Kyu-Myung Choi,
Jeong-Taek Kong,
Soo-Kwan Eo:
Runtime distribution-aware dynamic voltage scaling.
ICCAD 2006: 587-594 |
2005 |
30 | EE | Youngchul Cho,
Sungjoo Yoo,
Kiyoung Choi,
Nacer-Eddine Zergainoh,
Ahmed Amine Jerraya:
Scheduler implementation in MP SoC design.
ASP-DAC 2005: 151-156 |
29 | EE | Iuliana Bacivarov,
Aimen Bouchhima,
Sungjoo Yoo,
Ahmed Amine Jerraya:
ChronoSym: a new approach for fast and accurate SoC cosimulation.
IJES 1(1/2): 103-111 (2005) |
2004 |
28 | EE | Aimen Bouchhima,
Sungjoo Yoo,
Ahmed Amine Jerraya:
Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model.
ASP-DAC 2004: 469-474 |
27 | EE | Mohamed-Wassim Youssef,
Sungjoo Yoo,
Arif Sasongko,
Yanick Paviot,
Ahmed Amine Jerraya:
Debugging HW/SW interface for MPSoC: video encoder system design case study.
DAC 2004: 908-913 |
26 | EE | Sungjoo Yoo,
Mohamed-Wassim Youssef,
Aimen Bouchhima,
Ahmed Amine Jerraya,
Mario Diaz-Nava:
Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software.
DATE 2004: 1382-1383 |
2003 |
25 | EE | Sungjoo Yoo,
Ahmed Amine Jerraya:
Introduction to Hardware Abstraction Layers for SoC.
DATE 2003: 10336-10337 |
24 | EE | Sungjoo Yoo,
Iuliana Bacivarov,
Aimen Bouchhima,
Yanick Paviot,
Ahmed Amine Jerraya:
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer.
DATE 2003: 10550-10555 |
23 | EE | Youngchul Cho,
Ganghee Lee,
Sungjoo Yoo,
Kiyoung Choi,
Nacer-Eddine Zergainoh:
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
DATE 2003: 20132-20137 |
2002 |
22 | EE | Sunghyun Lee,
Sungjoo Yoo,
Kiyoung Choi:
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model.
CODES 2002: 199-204 |
21 | EE | Wander O. Cesário,
Amer Baghdadi,
Lovic Gauthier,
Damien Lyonnard,
Gabriela Nicolescu,
Yanick Paviot,
Sungjoo Yoo,
Ahmed Amine Jerraya,
Mario Diaz-Nava:
Component-based design approach for multicore SoCs.
DAC 2002: 789-794 |
20 | EE | Sungjoo Yoo,
Gabriela Nicolescu,
Lovic Gauthier,
Ahmed Amine Jerraya:
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design.
DATE 2002: 620-627 |
19 | EE | Sunghyun Lee,
Kiyoung Choi,
Sungjoo Yoo:
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model.
ISLPED 2002: 84-87 |
18 | EE | Ahmed Amine Jerraya,
Sungjoo Yoo,
Aimen Bouchhima,
Gabriela Nicolescu:
Validation in a Component-Based Design Flow for Multicore SoCs.
ISSS 2002: 162-167 |
17 | EE | Gabriela Nicolescu,
S. Martinez,
Lobna Kriaa,
Wassim Youssef,
Sungjoo Yoo,
Benoît Charlot,
Ahmed Amine Jerraya:
Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design.
VLSI Design 2002: 426- |
16 | EE | Wander O. Cesário,
Damien Lyonnard,
Gabriela Nicolescu,
Yanick Paviot,
Sungjoo Yoo,
Ahmed Amine Jerraya,
Lovic Gauthier,
Mario Diaz-Nava:
Multiprocessor SoC Platforms: A Component-Based Design Approach.
IEEE Design & Test of Computers 19(6): 52-63 (2002) |
15 | EE | Gabriela Nicolescu,
Kjetil Svarstad,
Wander O. Cesário,
Lovic Gauthier,
Damien Lyonnard,
Sungjoo Yoo,
Philippe Coste,
Ahmed Amine Jerraya:
Desiderata pour la spécification et la conception des systèmes électroniques.
Technique et Science Informatiques 21(3): 291-314 (2002) |
2001 |
14 | EE | Patrice Gerin,
Sungjoo Yoo,
Gabriela Nicolescu,
Ahmed Amine Jerraya:
Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures.
ASP-DAC 2001: 63-68 |
13 | EE | Sungjoo Yoo,
Gabriela Nicolescu,
Damien Lyonnard,
Amer Baghdadi,
Ahmed Amine Jerraya:
A generic wrapper architecture for multi-processor SoC cosimulation and design.
CODES 2001: 195-200 |
12 | EE | Damien Lyonnard,
Sungjoo Yoo,
Amer Baghdadi,
Ahmed Amine Jerraya:
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip.
DAC 2001: 518-523 |
11 | EE | Lovic Gauthier,
Sungjoo Yoo,
Ahmed Amine Jerraya:
Automatic generation and targeting of application specific operating systems and embedded systems software.
DATE 2001: 679-685 |
10 | EE | Jinyong Jung,
Sungjoo Yoo,
Kiyoung Choi:
Performance improvement of multi-processor systems cosimulation based on SW analysis.
DATE 2001: 749-753 |
9 | EE | Gabriela Nicolescu,
Sungjoo Yoo,
Ahmed Amine Jerraya:
Mixed-level cosimulation for fine gradual refinement of communication in SoC design.
DATE 2001: 754-759 |
8 | EE | Lovic Gauthier,
Sungjoo Yoo,
Ahmed Amine Jerraya:
Automatic generation and targeting of application-specificoperating systems and embedded systems software.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1293-1301 (2001) |
2000 |
7 | EE | Byungil Jeong,
Sungjoo Yoo,
Sunghyun Lee,
Kiyoung Choi:
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs.
ASP-DAC 2000: 169-174 |
6 | EE | Sungjoo Yoo,
Kyoungseok Rha,
Youngchul Cho,
Jinyong Jung,
Kiyoung Choi:
Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model.
CODES 2000: 77-81 |
5 | EE | Sungjoo Yoo,
Jong-eun Lee,
Jinyong Jung,
Kyungseok Rha,
Youngchul Cho,
Kiyoung Choi:
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor.
DATE 2000: 663-668 |
4 | EE | Sungjoo Yoo,
Kiyoung Choi,
Dong Sam Ha:
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages.
IEEE Trans. VLSI Syst. 8(5): 492-502 (2000) |
1999 |
3 | EE | Sungjoo Yoo,
Kiyoung Choi:
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages.
CODES 1999: 100-104 |
2 | EE | Byungil Jeong,
Sungjoo Yoo,
Kiyoung Choi:
Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design.
FPGA 1999: 247 |
1998 |
1 | EE | Sungjoo Yoo,
Kiyoung Choi:
Optimistic distributed timed cosimulation based on thread simulation model.
CODES 1998: 71-75 |