2005 |
21 | EE | Michael W. Beattie,
Hui Zheng,
Anirudh Devgan,
Byron Krauter:
Spatially distributed 3D circuit models.
DAC 2005: 153-158 |
20 | EE | Haihua Su,
David Widiger,
Chandramouli V. Kashyap,
Frank Liu,
Byron Krauter:
A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis.
DAC 2005: 186-189 |
19 | EE | Anirudh Devgan,
Luca Daniel,
Byron Krauter,
Lei He:
Modeling and Design of Chip-Package Interface.
ISQED 2005: 6 |
2003 |
18 | EE | Masud H. Chowdhury,
Chirayu S. Amin,
Yehea I. Ismail,
Chandramouli V. Kashyap,
Byron Krauter:
Realizable reduction of RLC circuits using node elimination.
ISCAS (3) 2003: 494-497 |
17 | EE | Hui Zheng,
Byron Krauter,
Lawrence T. Pileggi:
Electrical Modeling of Integrated-Package Power and Ground Distributions.
IEEE Design & Test of Computers 20(3): 24-31 (2003) |
2002 |
16 | EE | Byron Krauter,
David Widiger:
Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax.
DAC 2002: 665-668 |
15 | EE | Hui Zheng,
Lawrence T. Pileggi,
Michael W. Beattie,
Byron Krauter:
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses.
DATE 2002: 628-633 |
14 | EE | Masud H. Chowdhury,
Yehea I. Ismail,
Chandramouli V. Kashyap,
Byron Krauter:
Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance.
ISCAS (4) 2002: 197-200 |
13 | EE | James D. Warnock,
John M. Keaty,
John G. Petrovick,
Joachim G. Clabes,
Charles J. Kircher,
Byron Krauter,
Phillip Restle,
Brian A. Zoric,
Carl J. Anderson:
The circuit and physical design of the POWER4 microprocessor.
IBM Journal of Research and Development 46(1): 27-52 (2002) |
12 | EE | Yehea I. Ismail,
Byron Krauter:
Guest editorial: special issue on on-chip inductance in high-speed integrated circuits.
IEEE Trans. VLSI Syst. 10(6): 683-684 (2002) |
11 | EE | Gerard V. Kopcsay,
Byron Krauter,
David Widiger,
Alina Deutsch,
Barry J. Rubin,
H. H. Smith:
A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis.
IEEE Trans. VLSI Syst. 10(6): 695-711 (2002) |
2001 |
10 | EE | Michael W. Beattie,
Byron Krauter,
Lale Alatan,
Lawrence T. Pileggi:
Equipotential shells for efficient inductance extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 70-79 (2001) |
2000 |
9 | EE | Chandramouli V. Kashyap,
Byron Krauter:
A realizable driving point model for on-chip interconnect with inductance.
DAC 2000: 190-195 |
1998 |
8 | EE | Byron Krauter,
Sharad Mehrotra:
Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis.
DAC 1998: 303-308 |
1997 |
7 | EE | Rohini Gupta,
Byron Krauter,
Lawrence T. Pileggi:
Transmission line synthesis via constrained multivariable optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 6-19 (1997) |
1996 |
6 | EE | Byron Krauter,
Yu Xia,
E. Aykut Dengi,
Lawrence T. Pileggi:
A Sparse Image Method for BEM Capacitance Extraction.
DAC 1996: 357-362 |
5 | EE | Rohini Gupta,
Byron Krauter,
Lawrence T. Pileggi:
On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects.
VLSI Design 1996: 150-155 |
1995 |
4 | EE | Byron Krauter,
Rohini Gupta,
John Willis,
Lawrence T. Pileggi:
Transmission Line Synthesis.
DAC 1995: 358-363 |
3 | EE | Rohini Gupta,
Byron Krauter,
Bogdan Tutuianu,
John Willis,
Lawrence T. Pileggi:
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals.
DAC 1995: 364-369 |
2 | EE | Byron Krauter,
Lawrence T. Pileggi:
Generating sparse partial inductance matrices with guaranteed stability.
ICCAD 1995: 45-52 |
1993 |
1 | EE | S. Y. Kim,
Emre Tuncer,
Rohini Gupta,
Byron Krauter,
T. Savarino,
Dean P. Neikirk,
Lawrence T. Pillage:
An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules.
ICCAD 1993: 58-65 |