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Slawomir Pilarski

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2004
22EEDemos Anastasakis, Lisa McIlwain, Slawomir Pilarski: Efficient equivalence checking with partitions and hierarchical cut-points. DAC 2004: 539-542
2002
21EESlawomir Pilarski, Gracia Hu: SAT with partial clauses and back-leaps. DAC 2002: 743-746
20EESlawomir Pilarski, Gracia Hu: Speeding up SAT for EDA. DATE 2002: 1081
1997
19EEAlicja Pierzynska, Slawomir Pilarski: Pitfalls in delay fault testing. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 321-329 (1997)
1996
18EESandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma: Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503
1995
17EEAlicja Pierzynska, Slawomir Pilarski: Quality considerations in delay fault testing. EURO-DAC 1995: 196-201
16 Alicja Pierzynska, Slawomir Pilarski: Non-Robust versus Robust. ITC 1995: 123-131
15 Slawomir Pilarski, Kevin James Wiebe: Counter-Based Compaction: Delay and Stuck-Open Faults. IEEE Trans. Computers 44(6): 780-791 (1995)
14EESlawomir Pilarski: Comments on "Test efficiency analysis of random self-test of sequential circuits". IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 1044-1045 (1995)
13EESlawomir Pilarski: Comments on "Aliasing Properties of Circular MISRs". J. Electronic Testing 6(1): 139-140 (1995)
1994
12EESlawomir Pilarski, André Ivanov, Tiko Kameda: On minimizing aliasing in scan-based compaction. J. Electronic Testing 5(1): 83-90 (1994)
1993
11 Slawomir Pilarski, Alicja Pierzynska: BIST and Delay Fault Detection. ITC 1993: 236-242
10 Tiko Kameda, Slawomir Pilarski, André Ivanov: Notes on Multiple Input Signature Analysis. IEEE Trans. Computers 42(2): 228-234 (1993)
9EESlawomir Pilarski, Tiko Kameda, André Ivanov: Sequential faults and aliasing. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1068-1074 (1993)
8 Slawomir Pilarski, Tiko Kameda: Simple Bounds on the Convergence Rate of an Ergodic Markov Chain. Inf. Process. Lett. 45(2): 81-87 (1993)
1992
7 Andrzej Krasniewski, Slawomir Pilarski: High Quality Testing of Embedded RAMs Using Circular Self-Test Path. ITC 1992: 652-661
6EESlawomir Pilarski, Tiko Kameda: Checkpointing for Distributed Databases: Starting from the Basics. IEEE Trans. Parallel Distrib. Syst. 3(5): 602-610 (1992)
5EESlawomir Pilarski, Andrzej Krasniewski, Tiko Kameda: Estimating testing effectiveness of the circular self-test path technique. IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1301-1316 (1992)
4EESlawomir Pilarski, Kevin James Wiebe: Counter-based compaction: An analysis for BIST. J. Electronic Testing 3(1): 33-43 (1992)
1990
3EESlawomir Pilarski, Tiko Kameda: A Novel Checkpointing Scheme for Distributed Database Systems. PODS 1990: 368-378
1989
2EEAndrzej Krasniewski, Slawomir Pilarski: Circular self-test path: a low-cost BIST technique for VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 8(1): 46-55 (1989)
1987
1EEAndrzej Krasniewski, Slawomir Pilarski: Circular Self-Test Path: A Low-Cost BIST Technique. DAC 1987: 407-415

Coauthor Index

1Demos Anastasakis [22]
2Sandeep K. Gupta [18]
3Gracia Hu [20] [21]
4André Ivanov [9] [10] [12]
5Tiko Kameda [3] [5] [6] [8] [9] [10] [12]
6Andrzej Krasniewski [1] [2] [5] [7]
7Lisa McIlwain [22]
8Alicja Pierzynska [11] [16] [17] [19]
9Sudhakar M. Reddy [18]
10Jacob Savir [18]
11Prab Varma [18]
12Kevin James Wiebe [4] [15]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)