2008 | ||
---|---|---|
37 | EE | M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre: AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. DELTA 2008: 314-321 |
36 | EE | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: An Integrated Validation Environment for Differential Power Analysis. DELTA 2008: 527-532 |
35 | EE | Julien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre: Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI 2008: 139-144 |
2007 | ||
34 | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: A Novel Parity Bit Scheme for SBox in AES Circuits. DDECS 2007: 267-271 | |
33 | EE | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS 2007: 57-62 |
32 | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: A Dependable Parallel Architecture for SBoxes. ReCoSoC 2007: 132-137 | |
31 | EE | Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Test data compression and TAM design. VLSI-SoC 2007: 178-183 |
30 | EE | Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre: Mutation Sampling Technique for the Generation of Structural Test Data CoRR abs/0710.4802: (2007) |
29 | EE | David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Securing Scan Control in Crypto Chips. J. Electronic Testing 23(5): 457-464 (2007) |
2006 | ||
28 | EE | David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: A secure scan design methodology. DATE 2006: 1177-1178 |
27 | EE | Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA 2006: 295-300 |
26 | EE | David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Secure Scan Techniques: A Comparison. IOLTS 2006: 119-124 |
2005 | ||
25 | EE | Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre: Mutation Sampling Technique for the Generation of Structural Test Data. DATE 2005: 1022-1023 |
2004 | ||
24 | EE | Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre: An Arithmetic Structure for Test Data Horizontal Compression. DATE 2004: 428-435 |
23 | EE | Marie-Lise Flottes, Yves Bertrand, L. Balado, E. Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich: Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. DELTA 2004: 135-139 |
22 | EE | Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre: On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA 2004: 275-280 |
21 | EE | David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell: Scan Design and Secure Chip. IOLTS 2004: 219-226 |
2003 | ||
20 | EE | Yves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden: Test Engineering Education in Europe: the EuNICE-Test Project. MSE 2003: 85-86 |
19 | EE | Marie-Lise Flottes, Christian Landrault, A. Petitqueux: A Unified DFT Approach for BIST and External Test. J. Electronic Testing 19(1): 49-60 (2003) |
2002 | ||
18 | Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes: SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France Kluwer 2002 | |
17 | EE | Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre: A Heuristic for Test Scheduling at System Level. DATE 2002: 1124 |
16 | EE | Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, Regis Lorival: European Network for Test Education. DELTA 2002: 230-234 |
2001 | ||
15 | Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre: Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. VLSI-SOC 2001: 401-412 | |
14 | EE | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis. J. Electronic Testing 17(3-4): 331-339 (2001) |
2000 | ||
13 | EE | Marie-Lise Flottes, Christian Landrault, A. Petitqueux: Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Asian Test Symposium 2000: 404- |
12 | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: BISTing data paths at behavioral level. ITC 2000: 672-680 | |
1999 | ||
11 | EE | Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival: A Successful Distance-Learning Experience for IC Test Education. MSE 1999: 20-21 |
10 | EE | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: BISTing Datapaths under Heterogeneous Test Schemes. J. Electronic Testing 14(1-2): 115-123 (1999) |
1998 | ||
9 | EE | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre: Alleviating DFT Cost Using Testability Driven HLS. Asian Test Symposium 1998: 46-51 |
8 | EE | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. DATE 1998: 921-922 |
7 | EE | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Low Cost Partial Scan Design: A High Level Synthesis Approach. VTS 1998: 332-340 |
1997 | ||
6 | EE | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre: Analyzing testability from behavioral to RT level. ED&TC 1997: 158-165 |
5 | EE | Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre: Improving Testability of Non-Scan Designs during Behavioral Synthesis. J. Electronic Testing 11(1): 29-42 (1997) |
1995 | ||
4 | Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre: Is High-Level Test Synthesis Just Design for Test? ITC 1995: 294 | |
1994 | ||
3 | Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre: Automatic Synthesis of BISTed Data Paths From High Level Specification. EDAC-ETC-EUROASIC 1994: 591-598 | |
1991 | ||
2 | EE | Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch: Fault modeling and fault equivalence in CMOS technology. J. Electronic Testing 2(3): 229-241 (1991) |
1990 | ||
1 | EE | Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch: Fault modelling and fault equivalence in CMOS technology. EURO-DAC 1990: 407-412 |