Dariusz Kania

2007
9	EE	Dariusz Kania: A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS. ACM Great Lakes Symposium on VLSI 2007: 152-155
8	EE	Dariusz Kania, Józef Kulisz: Logic synthesis for PAL-based CPLD-s based on two-stage decomposition. Journal of Systems and Software 80(7): 1129-1141 (2007)
2005
7	EE	Dariusz Kania, Józef Kulisz, Adam Milik: A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. DSD 2005: 114-121
6	EE	Robert Czerwinski, Dariusz Kania: State Assignment for PAL-based CPLDs. DSD 2005: 127-134
5	EE	Dariusz Kania, Adam Milik, Józef Kulisz: Decomposition of Multi-Output Functions for CPLDs. DSD 2005: 442-449
2002
4	EE	Dariusz Kania: Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions. DATE 2002: 1087
2000
3	EE	Dariusz Kania: Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping. EUROMICRO 2000: 1138-1145
2	EE	Dariusz Kania: A Technology Mapping Algorithm for PAL-Based Devices Using Multi-Output Function Graphs. EUROMICRO 2000: 1146-
1999
1	EE	Dariusz Kania: Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition. EUROMICRO 1999: 1278-1281

Coauthor Index

1	Robert Czerwinski	[6]
2	Józef Kulisz	[5] [7] [8]
3	Adam Milik	[5] [7]

Colors in the list of coauthors