2005 |
12 | EE | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver:
A Coarse-Grain Phased Logic CPU.
IEEE Trans. Computers 54(7): 788-799 (2005) |
11 | EE | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver,
David Hemmendinger:
Early evaluation for performance enhancement in phased logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 532-550 (2005) |
2004 |
10 | EE | Kenneth Fazel,
Lun Li,
Mitchell A. Thornton,
Robert B. Reese,
Cherrice Traver:
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion.
ACM Great Lakes Symposium on VLSI 2004: 413-416 |
2003 |
9 | EE | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver:
A Coarse-Grain Phased Logic CPU.
ASYNC 2003: 2-13 |
8 | EE | Kenneth Fazel,
Mitchell A. Thornton,
Robert B. Reese:
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs.
DATE 2003: 11096-11097 |
7 | EE | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver:
A Fine-Grain Phased Logic CPU.
ISVLSI 2003: 70-79 |
2002 |
6 | EE | Mitchell A. Thornton,
Kenneth Fazel,
Robert B. Reese,
Cherrice Traver:
Generalized Early Evaluation in Self-Timed Circuits.
DATE 2002: 255-259 |
2001 |
5 | | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver:
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation.
ICCD 2001: 18-23 |
2000 |
4 | EE | Hemang Lavana,
Franc Brglez,
Robert B. Reese,
Gangadhar Konduri,
Anantha Chandrakasan:
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet.
ICCD 2000: 567-570 |
1999 |
3 | EE | Hemang Lavana,
Franc Brglez,
Robert B. Reese:
User-configurable experimental design flows on the web: the ISCAS'99 experiments.
ISCAS (6) 1999: 440-443 |
1997 |
2 | EE | J. Scott Calhoun,
Vijay K. Madisetti,
Robert B. Reese,
Thomas Egolf:
Developing and Distributing Component-Level VHDL Models.
VLSI Signal Processing 15(1-2): 111-126 (1997) |
1993 |
1 | | Richard Auletta,
Robert B. Reese,
Cherrice Traver:
A Comparison of Synchronous and Asynchronous FSMD Designs.
ICCD 1993: 178-182 |