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Maria J. Avedillo

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2008
31EEHéctor Pettenghi, Maria J. Avedillo, José M. Quintana: A novel contribution to the RTD-based threshold logic family. ISCAS 2008: 2350-2353
30EEJuan Núñez, José M. Quintana, Maria J. Avedillo: Limits to a correct operation in RTD-based ternary inverters. ISCAS 2008: 604-607
2007
29EEJuan Núñez, José M. Quintana, Maria J. Avedillo: Operation limits in RTD-based ternary quantizers. ACM Great Lakes Symposium on VLSI 2007: 114-119
28EEHéctor Pettenghi, Maria J. Avedillo, José M. Quintana: Non Return Mobile Logic Family. ISCAS 2007: 125-128
27EEJuan Núñez, José M. Quintana, Maria J. Avedillo: Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. ISMVL 2007: 51
26EEJuan Núñez, José M. Quintana, Maria J. Avedillo: A quasi-differential quantizer based on SMOBILE. SBCCI 2007: 251-256
2006
25EEJosé M. Quintana, Maria J. Avedillo, Juan Núñez: Design Guides for a Correct DC Operation in RTD-based Threshold Gates. DSD 2006: 530-536
24EEJosé M. Quintana, Maria J. Avedillo, Héctor Pettenghi: Self-latching operation limits for MOBILE circuits. ISCAS 2006
2005
23EEMaria J. Avedillo, José M. Quintana, Héctor Pettenghi: Logic Models Supporting the Design of MOBILE-based RTD Circuits. ASAP 2005: 254-259
22EEMaria J. Avedillo, José M. Quintana, José L. Huertas: Robust frequency divider based on resonant tunneling devices. ISCAS (3) 2005: 2647-2650
2004
21EEMaria J. Avedillo, José M. Quintana: A Threshold Logic Synthesis Tool for RTD Circuits. DSD 2004: 624-627
20 José M. Quintana, Maria J. Avedillo, Héctor Pettenghi: Programmable logic gate based on resonant tunnelling devices. ISCAS (3) 2004: 697-700
19EEMaria J. Avedillo, José M. Quintana, Raúl Jiménez-Naharro: Pass-transistor based implementations of threshold logic gates for WOS filtering. Microelectronics Journal 35(11): 869-873 (2004)
18EEMaria J. Avedillo, José M. Quintana, Hamid El Alami, Antonio Jiménez-Calderón: A Practical Parallel Architecture for Stacks Filters. VLSI Signal Processing 38(2): 91-100 (2004)
2003
17EEValeriu Beiu, Maria J. Avedillo, José M. Quintana: Review of Capacitive Threshold Gate Implementations. ICANN 2003: 737-744
16 Valeriu Beiu, José M. Quintana, Maria J. Avedillo: Review of Differential Threshold Gate Implementations. Neural Networks and Computational Intelligence 2003: 44-49
2002
15EEManuel Martínez, Maria J. Avedillo, José M. Quintana, H. Süß, Manfred Koegst: An Encoding Technique for Low Power CMOS Implementations of Controllers. DATE 2002: 1083
14EEJosé M. Quintana, Maria J. Avedillo, José L. Huertas: Simplified Reed-Muller expressions for residue threshold functions. ISCAS (4) 2002: 599-602
13EEMaria J. Avedillo, José M. Quintana, Esther Rodríguez-Villegas: Simple parallel weighted order statistic filter implementations. ISCAS (4) 2002: 607-610
12EEEsther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda: High-speed low-power logic gates using floating gates. ISCAS (5) 2002: 389-392
2001
11EEJosé M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas: Practical low-cost CPL implementations threshold logic functions. ACM Great Lakes Symposium on VLSI 2001: 139-144
10EEManfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo: Two-Criterial Constraint-Driven FSM State Encoding for Low Power. DSD 2001: 94-101
9EEJosé M. Quintana, Maria J. Avedillo: Reed-Muller descriptions of symmetric functions. ISCAS (4) 2001: 682-685
8EEJosé M. Quintana, Maria J. Avedillo, José Luis Huertas: Efficient Realization of a Threshold Voter for Self-Purging Redundancy. J. Electronic Testing 17(1): 69-73 (2001)
1999
7EEManuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas: An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. DATE 1999: 521-525
6EEEsther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda: vMOS-based sorters for multiplier implementations. ISCAS (1) 1999: 338-341
1998
5EEManuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas: A Dynamic Model for the State Assignment Problem. DATE 1998: 835-839
1995
4EEJosé M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas: Optimum PLA folding through boolean satisfiability. ASP-DAC 1995
3EEMaria J. Avedillo, José M. Quintana, José Luis Huertas: Constrained state assignment of easily testable FSMs. J. Electronic Testing 6(1): 133-138 (1995)
1993
2 Maria J. Avedillo, José M. Quintana, José L. Huertas: Easily Testable PLA-based FSMS. ISCAS 1993: 1603-1606
1990
1EEMaria J. Avedillo, José M. Quintana, José Luis Huertas: A new method for the state reduction of incompletely specified finite sequential machines. EURO-DAC 1990: 552-556

Coauthor Index

1Hamid El Alami [18]
2Valeriu Beiu [16] [17]
3Günter Franke [10]
4Gloria Huertas [6]
5José Luis Huertas (José L. Huertas) [1] [2] [3] [4] [5] [7] [8] [14] [22]
6Raúl Jiménez [11]
7Antonio Jiménez-Calderón [18]
8Raúl Jiménez-Naharro [19]
9Manfred Koegst [10] [15]
10Manuel Martínez [5] [7] [15]
11Juan Núñez [25] [26] [27] [29] [30]
12Maria P. Parra [4]
13Héctor Pettenghi [20] [23] [24] [28] [31]
14José M. Quintana [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31]
15Esther Rodríguez-Villegas [6] [11] [12] [13]
16Adoración Rueda [6] [12]
17Steffen Rülke [10]
18H. Süß [15]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)