| 2008 |
|---|
| 21 | EE | Neal Tew,
Priyank Kalla,
Namrata Shekhar,
Sivaram Gopalakrishnan:
Verification of arithmetic datapaths using polynomial function models and congruence solving.
ICCAD 2008: 122-128 |
| 20 | EE | Namrata Shekhar,
Priyank Kalla,
M. Brandon Meredith,
Florian Enescu:
Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra.
IEEE Trans. VLSI Syst. 16(4): 376-387 (2008) |
| 2007 |
|---|
| 19 | EE | Sivaram Gopalakrishnan,
Priyank Kalla,
Florian Enescu:
Optimization of Arithmetic Datapaths with Finite Word-Length Operands.
ASP-DAC 2007: 511-516 |
| 18 | EE | Sivaram Gopalakrishnan,
Priyank Kalla,
M. Brandon Meredith,
Florian Enescu:
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors.
ICCAD 2007: 143-148 |
| 17 | EE | Christopher Condrat,
Priyank Kalla:
A Gröbner Basis Approach to CNF-Formulae Preprocessing.
TACAS 2007: 618-631 |
| 16 | EE | Sivaram Gopalakrishnan,
Priyank Kalla:
Optimization of polynomial datapaths using finite ring algebra.
ACM Trans. Design Autom. Electr. Syst. 12(4): (2007) |
| 2006 |
|---|
| 15 | EE | Namrata Shekhar,
Priyank Kalla,
Florian Enescu:
Equivalence verification of arithmetic datapaths with multiple word-length operands.
DATE 2006: 824-829 |
| 14 | EE | Namrata Shekhar,
Priyank Kalla,
M. Brandon Meredith,
Florian Enescu:
Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands.
FMCAD 2006: 179-186 |
| 13 | EE | Maciej J. Ciesielski,
Priyank Kalla,
Serkan Askar:
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs.
IEEE Trans. Computers 55(9): 1188-1201 (2006) |
| 2005 |
|---|
| 12 | | Namrata Shekhar,
Priyank Kalla,
Florian Enescu,
Sivaram Gopalakrishnan:
Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra.
ICCAD 2005: 291-296 |
| 11 | EE | Namrata Shekhar,
Priyank Kalla,
Sivaram Gopalakrishnan,
Florian Enescu:
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths.
ICCD 2005: 215-220 |
| 10 | EE | Vijay Durairaj,
Priyank Kalla:
Variable Ordering for Efficient SAT Search by Analyzing Constraint-Variable Dependencies.
SAT 2005: 415-422 |
| 2004 |
|---|
| 9 | EE | Vijay Durairaj,
Priyank Kalla:
Guiding CNF-SAT search via efficient constraint partitioning.
ICCAD 2004: 498-501 |
| 2002 |
|---|
| 8 | EE | Maciej J. Ciesielski,
Priyank Kalla,
Zhihong Zeng,
Bruno Rouzeyre:
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification.
DATE 2002: 285-291 |
| 7 | EE | Navin Vemuri,
Priyank Kalla,
Russell Tessier:
BDD-based logic synthesis for LUT-based FPGAs.
ACM Trans. Design Autom. Electr. Syst. 7(4): 501-525 (2002) |
| 6 | EE | Priyank Kalla,
Maciej J. Ciesielski:
A comprehensive approach to the partial scan problem using implicitstate enumeration.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 810-826 (2002) |
| 2001 |
|---|
| 5 | EE | Zhihong Zeng,
Priyank Kalla,
Maciej J. Ciesielski:
LPSAT: a unified approach to RTL satisfiability.
DATE 2001: 398-402 |
| 2000 |
|---|
| 4 | EE | Priyank Kalla,
Zhihong Zeng,
Maciej J. Ciesielski,
ChiLai Huang:
A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm.
DATE 2000: 232-236 |
| 1999 |
|---|
| 3 | EE | Priyank Kalla,
Maciej J. Ciesielski:
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence.
DATE 1999: 638-642 |
| 1998 |
|---|
| 2 | EE | Priyank Kalla,
Maciej J. Ciesielski:
A comprehensive approach to the partial scan problem using implicit state enumeration.
ITC 1998: 651-657 |
| 1997 |
|---|
| 1 | EE | Priyank Kalla,
Maciej J. Ciesielski:
Testability of Sequential Circuits with Multi-Cycle False Path.
VTS 1997: 322-328 |
