Yiran Chen

2009
17	EE	Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen: A novel architecture of the 3D stacked MRAM L2 cache for CMPs. HPCA 2009: 239-249
2008
16	EE	Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Helen Li, Yiran Chen: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC 2008: 554-559
15	EE	Wei Xu, Tong Zhang, Yiran Chen: Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin. ISCAS 2008: 1898-1901
14	EE	Yiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimitar V. Dimitrov: Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM). ISQED 2008: 684-690
2007
13	EE	Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li: VOSCH: Voltage scaled cache hierarchies. ICCD 2007: 496-503
12	EE	Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh: Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. ISLPED 2007: 195-200
11	EE	Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical Timing Analysis Considering Spatial Correlations. ISQED 2007: 102-107
2006
10	EE	Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh: SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163
2005
9		Wai-Ching Douglas Lam, J. Jam, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical based link insertion for robust clock network design. ICCAD 2005: 588-591
8	EE	Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ISLPED 2005: 115-118
7	EE	Dongku Kang, Yiran Chen, Kaushik Roy: Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. ISQED 2005: 48-53
6	EE	Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. VLSI Syst. 13(1): 75-85 (2005)
2004
5	EE	Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898
4		Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar: DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. VLSI Syst. 12(3): 245-254 (2004)
2003
3	EE	Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy: Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-
2	EE	Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234
2002
1	EE	Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy: Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-937

Coauthor Index

1	Venkataramanan Balakrishnan	[1] [9] [11]
2	Swarup Bhunia	[3] [4]
3	Dimitar V. Dimitrov	[14]
4	Xiangyu Dong	[16] [17]
5	J. Jam	[9]
6	Dongku Kang	[7]
7	Cheng-Kok Koh	[1] [2] [5] [6] [8] [9] [10] [11] [12] [13]
8	Wai-Ching Douglas Lam	[9]
9	Hai Li	[3] [4] [8] [10] [12] [13] [14]
10	Helen Li	[16]
11	Hong Li	[11]
12	Jian Li	[17]
13	Jing Li	[12]
14	Harry Liu	[14]
15	Kaushik Roy	[1] [2] [3] [4] [5] [6] [7] [8] [10]
16	Guangyu Sun	[16] [17]
17	T. N. Vijaykumar	[3] [4]
18	Xiaobin Wang	[14]
19	Weng-Fai Wong	[13]
20	Xiaoxia Wu	[16]
21	Yuan Xie	[16] [17]
22	Wei Xu	[15]
23	Tong Zhang	[15]