2005 |
25 | EE | Ismet Bayraktaroglu,
Olivier Caty,
Yickkei Wong:
Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories.
VTS 2005: 21-26 |
24 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations.
IEEE Trans. Computers 54(1): 61-75 (2005) |
2004 |
23 | EE | Sule Ozev,
Ismet Bayraktaroglu,
Alex Orailoglu:
Seamless Test of Digital Components in Mixed-Signal Paths.
IEEE Design & Test of Computers 21(1): 44-55 (2004) |
22 | EE | Yiorgos Makris,
Ismet Bayraktaroglu,
Alex Orailoglu:
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.
IEEE Transactions on Reliability 53(2): 269-278 (2004) |
2003 |
21 | EE | Wenjing Rao,
Ismet Bayraktaroglu,
Alex Orailoglu:
Test application time and volume compression through seed overlapping.
DAC 2003: 732-737 |
20 | EE | Olivier Caty,
Ismet Bayraktaroglu,
Amitava Majumdar,
Richard Lee,
John Bell,
Lisa Curhan:
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects.
ITC 2003: 961-970 |
19 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression.
VTS 2003: 113-120 |
18 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs.
IEEE Trans. Computers 52(11): 1480-1489 (2003) |
17 | EE | Ozgur Sinanoglu,
Ismet Bayraktaroglu,
Alex Orailoglu:
Reducing Average and Peak Test Power Through Scan Chain Modification.
J. Electronic Testing 19(4): 457-467 (2003) |
2002 |
16 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Gate Level Fault Diagnosis in Scan-Based BIST.
DATE 2002: 376-381 |
15 | EE | Ozgur Sinanoglu,
Ismet Bayraktaroglu,
Alex Orailoglu:
Scan Power Reduction Through Test Data Transition Frequency Analysis.
ITC 2002: 844-850 |
14 | EE | Ozgur Sinanoglu,
Ismet Bayraktaroglu,
Alex Orailoglu:
Test Power Reduction through Minimization of Scan Chain Transitions.
VTS 2002: 166-172 |
13 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST.
IEEE Design & Test of Computers 19(1): 42-53 (2002) |
2001 |
12 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?
Asian Test Symposium 2001: 373-378 |
11 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Test Volume and Application Time Reduction Through Scan Chain Concealment.
DAC 2001: 151-155 |
10 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Diagnosis for scan-based BIST: reaching deep into the signatures.
DATE 2001: 102-111 |
9 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Concurrent test for digital linear systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1132-1142 (2001) |
2000 |
8 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Accumulation-based concurrent fault detection for linear digital state variable systems.
Asian Test Symposium 2000: 484- |
7 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Improved fault diagnosis in scan-based BIST via superposition.
DAC 2000: 55-58 |
6 | EE | Sule Ozev,
Ismet Bayraktaroglu,
Alex Orailoglu:
Test Synthesis for Mixed-Signal SOC Paths.
DATE 2000: 128-133 |
5 | | Ismet Bayraktaroglu,
Alex Orailoglu:
Deterministic partitioning techniques for fault diagnosis in scan-based BIST.
ITC 2000: 273-282 |
4 | EE | Yiorgos Makris,
Ismet Bayraktaroglu,
Alex Orailoglu:
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits.
VTS 2000: 459-464 |
1999 |
3 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Low-Cost On-Line Test for Digital Filters.
VTS 1999: 446-451 |
2 | EE | Ismet Bayraktaroglu,
Arif Selçuk Ögrenci,
Günhan Dündar,
Sina Balkir,
Ethem Alpaydin:
ANNSyS: an Analog Neural Network Synthesis System.
Neural Networks 12(2): 325-338 (1999) |
1998 |
1 | EE | Ismet Bayraktaroglu,
K. Udawatta,
Alex Orailoglu:
An Examination of PRPG Selection Approaches for Large, Industrial Designs.
Asian Test Symposium 1998: 440- |