2008 |
21 | EE | Seong-Ook Jung,
Sei-Seung Yoon:
Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory.
IEICE Transactions 91-A(3): 895-898 (2008) |
2007 |
20 | EE | Myeong-Eun Hwang,
Seong-Ook Jung,
Kaushik Roy:
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.
ISLPED 2007: 387-390 |
2005 |
19 | EE | Ge Yang,
Seong-Ook Jung,
Kwang-Hyun Baek,
Soo Hwan Kim,
Suki Kim,
Sung-Mo Kang:
A 32-bit carry lookahead adder using dual-path all-N logic.
IEEE Trans. VLSI Syst. 13(8): 992-996 (2005) |
2004 |
18 | | Ge Yang,
Seong-Ook Jung,
Kwang-Hyun Baek,
Soo Hwan Kim,
Suki Kim,
Sung-Mo Kang:
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.
ISCAS (2) 2004: 781-784 |
2003 |
17 | EE | Ki-Wook Kim,
Seong-Ook Jung,
Taewhan Kim,
Sung-Mo Kang:
Minimum delay optimization for domino circuits - a coupling-aware approach.
ACM Trans. Design Autom. Electr. Syst. 8(2): 202-213 (2003) |
16 | EE | Ki-Wook Kim,
Seong-Ook Jung,
Unni Narayanan,
C. L. Liu,
Sung-Mo Kang:
Noise-aware interconnect power optimization in domino logic synthesis.
IEEE Trans. VLSI Syst. 11(1): 79-89 (2003) |
15 | EE | Ki-Wook Kim,
Seong-Ook Jung,
Taewhan Kim,
Prashant Saxena,
C. L. Liu,
S.-M. S. Kang:
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.
IEEE Trans. VLSI Syst. 11(5): 879-887 (2003) |
14 | EE | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Timing constraints for domino logic gates with timing-dependent keepers.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 96-103 (2003) |
2002 |
13 | EE | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Low-swing clock domino logic incorporating dual supply and dual threshold voltages.
DAC 2002: 467-472 |
12 | EE | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.
DATE 2002: 260-267 |
11 | EE | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Optimal Timing for Skew-Tolerant High-Speed Domino Logic.
ISVLSI 2002: 41-46 |
10 | EE | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Noise constrained transistor sizing and power optimization for dual Vst domino logic.
IEEE Trans. VLSI Syst. 10(5): 532-541 (2002) |
2001 |
9 | EE | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Transistor sizing for reliable domino logic design in dual threshold voltage technologies.
ACM Great Lakes Symposium on VLSI 2001: 133-138 |
8 | EE | Seung-Moon Yoo,
Seong-Ook Jung,
Sung-Mo Kang:
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test.
ACM Great Lakes Symposium on VLSI 2001: 93-96 |
7 | EE | Ki-Wook Kim,
Seong-Ook Jung,
Prashant Saxena,
C. L. Liu,
Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.
DAC 2001: 732-737 |
6 | EE | Seung-Moon Yoo,
Seong-Ook Jung,
Sung-Mo Kang:
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT.
ISCAS (4) 2001: 1-4 |
5 | EE | Seong-Ook Jung,
Seung-Moon Yoo,
Ki-Wook Kim,
Sung-Mo Kang:
Skew-tolerant high-speed (STHS) domino logic.
ISCAS (4) 2001: 154-157 |
4 | EE | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Noise constrained power optimization for dual VT domino logic.
ISCAS (4) 2001: 158-161 |
3 | EE | Seung-Moon Yoo,
Chulwoo Kim,
Seong-Ook Jung,
Kwang-Hyun Baek,
Sung-Mo Kang:
New current-mode sense amplifiers for high density DRAM and PIM architectures.
ISCAS (4) 2001: 938-941 |
2 | EE | Ki-Wook Kim,
Seong-Ook Jung,
Sung-Mo Kang:
Coupling-aware minimum delay optimization for domino logic circuits.
ISCAS (5) 2001: 371-374 |
2000 |
1 | EE | Ki-Wook Kim,
Seong-Ook Jung,
Unni Narayanan,
C. L. Liu,
Sung-Mo Kang:
Noise-aware power optimization for on-chip interconnect.
ISLPED 2000: 108-113 |