2007 |
25 | EE | Nikolaos Andrikos,
Luciano Lavagno,
Davide Pandini,
Christos P. Sotiriou:
A Fully-Automated Desynchronization Flow for Synchronous Circuits.
DAC 2007: 982-985 |
24 | EE | Cristiano Forzan,
Davide Pandini:
Why we need statistical static timing analysis.
ICCD 2007: 91-96 |
23 | EE | Davide Pandini:
Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies.
IOLTS 2007: 254 |
22 | EE | Angelo P. E. Rosiello,
Fabrizio Ferrandi,
Davide Pandini,
Donatella Sciuto:
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis.
ISVLSI 2007: 92-97 |
21 | EE | Davide Pandini,
Guido A. Repetto,
Vincenzo Sinisi:
Clock Distribution Techniques for Low-EMI Design.
PATMOS 2007: 201-210 |
20 | EE | Davide Pandini:
Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies.
PATMOS 2007: 577 |
19 | EE | Davide Pandini,
Giuseppe Desoli,
Alessandro Cremonesi:
Computing and design for software and silicon manufacturing.
VLSI-SoC 2007: 122-127 |
18 | EE | Cristiano Forzan,
Davide Pandini:
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis
CoRR abs/0710.4639: (2007) |
2006 |
17 | EE | L. Necchi,
Luciano Lavagno,
Davide Pandini,
Laura Vanzago:
An ultra-low energy asynchronous processor for Wireless Sensor Networks.
ASYNC 2006: 78-85 |
16 | EE | Davide Pandini,
Guido A. Repetto:
Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design.
PATMOS 2006: 532-542 |
15 | EE | Cristiano Forzan,
Davide Pandini,
Mariagrazia Graziano:
Power Supply Selective Mapping for Accurate Timing Analysis.
J. Low Power Electronics 2(1): 105-112 (2006) |
2005 |
14 | EE | Cristiano Forzan,
Davide Pandini:
A complete methodology for an accurate static noise analysis.
ACM Great Lakes Symposium on VLSI 2005: 302-307 |
13 | EE | Cristiano Forzan,
Davide Pandini:
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis.
DATE 2005: 982-983 |
12 | EE | Mariagrazia Graziano,
Cristiano Forzan,
Davide Pandini:
Power Supply Selective Mapping for Accurate Timing Analysis.
PATMOS 2005: 267-276 |
2004 |
11 | EE | Luca Macchiarulo,
Consolato F. Caccamo,
Davide Pandini:
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures.
ACM Great Lakes Symposium on VLSI 2004: 436-439 |
10 | EE | Davide Pandini,
Cristiano Forzan,
Livio Baldi:
Design Methodologies and Architecture Solutions for High-Performance Interconnects.
ICCD 2004: 152-159 |
2003 |
9 | EE | Davide Pandini,
Lawrence T. Pileggi,
Andrzej J. Strojwas:
Bounding the efforts on congestion optimization for physical synthesis.
ACM Great Lakes Symposium on VLSI 2003: 7-10 |
8 | EE | Davide Pandini,
Lawrence T. Pileggi,
Andrzej J. Strojwas:
Global and local congestion optimization in technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 498-505 (2003) |
2002 |
7 | EE | Davide Pandini,
Lawrence T. Pileggi,
Andrzej J. Strojwas:
Congestion-Aware Logic Synthesis.
DATE 2002: 664-671 |
6 | EE | Davide Pandini,
Lawrence T. Pileggi,
Andrzej J. Strojwas:
Understanding and addressing the impact of wiring congestion during technology mapping.
ISPD 2002: 131-136 |
2000 |
5 | EE | Bruno Franzini,
Cristiano Forzan,
Davide Pandini,
Primo Scandolara,
Alessandro Dal Fabbro:
Crosstalk Aware Static Timing Analysis: A Two Step Approach.
ISQED 2000: 499-504 |
1998 |
4 | | Davide Pandini,
Primo Scandolara,
Carlo Guardiani:
Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs.
ASP-DAC 1998: 45-50 |
1995 |
3 | EE | Enrico Malavasi,
Davide Pandini:
Optimum CMOS stack generation with analog constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 107-122 (1995) |
1994 |
2 | EE | Edoardo Charbon,
Enrico Malavasi,
Davide Pandini,
Alberto L. Sangiovanni-Vincentelli:
Simultaneous Placement and Module Optimization of Analog IC's.
DAC 1994: 31-35 |
1993 |
1 | | Valentino Liberali,
Enrico Malavasi,
Davide Pandini:
Automatic Generation of Transistor Stacks for CMOS Analog Layout.
ISCAS 1993: 2098-2102 |