2007 | ||
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37 | EE | Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar: AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ASP-DAC 2007: 823-828 |
36 | EE | Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah: Variation-aware performance verification using at-speed structural test and statistical timing. ICCAD 2007: 405-412 |
35 | EE | Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland: An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. VTS 2007: 173-178 |
2006 | ||
34 | EE | Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich: Performance verification of high-performance ASICs using at-speed structural test. ACM Great Lakes Symposium on VLSI 2006: 247-252 |
33 | EE | Vikram Iyengar, Gary Grise, Mark Taylor: A flexible and scalable methodology for GHz-speed structural test. DAC 2006: 314-319 |
32 | EE | Chunsheng Liu, Vikram Iyengar: Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. DATE 2006: 652-657 |
31 | EE | Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan: Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. VTS 2006: 46-51 |
2005 | ||
30 | EE | Vikram Iyengar, Phil Nigh: Defect-Oriented Test for Ultra-Low DPM. Asian Test Symposium 2005: 455 |
29 | EE | Chunsheng Liu, Kugesh Veeraraghavant, Vikram Iyengar: Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems. DFT 2005: 552-562 |
28 | EE | Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota: Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. VTS 2005: 349-354 |
27 | EE | Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski: Test planning for modular testing of hierarchical SOCs. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 435-448 (2005) |
2004 | ||
26 | EE | Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty: SOC test planning using virtual test access architectures. IEEE Trans. VLSI Syst. 12(12): 1263-1276 (2004) |
2003 | ||
25 | EE | Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty: Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. DAC 2003: 738-743 |
24 | EE | Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty: A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. DATE 2003: 11188-11190 |
23 | EE | Vikram Iyengar, Anshuman Chandra: A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. DFT 2003: 511-518 |
22 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar: Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. VTS 2003: 299-312 |
21 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. IEEE Trans. Computers 52(12): 1619-1632 (2003) |
20 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Efficient test access mechanism optimization for system-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 635-643 (2003) |
2002 | ||
19 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. Asian Test Symposium 2002: 320- |
18 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. DAC 2002: 685-690 |
17 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Efficient Wrapper/TAM Co-Optimization for Large SOCs. DATE 2002: 491-498 |
16 | EE | Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC 2002: 1159-1168 |
15 | EE | Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty: A Set of Benchmarks fo Modular Testing of SOCs. ITC 2002: 519-528 |
14 | EE | Sandeep Koranne, Vikram Iyengar: On the Use of k-tuples for SoC Test Schedule Representation. ITC 2002: 539-548 |
13 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. VTS 2002: 253-258 |
12 | EE | Vikram Iyengar, Krishnendu Chakrabarty: Test Bus Sizing for System-on-a-Chip. IEEE Trans. Computers 51(5): 449-459 (2002) |
11 | EE | Vikram Iyengar, Krishnendu Chakrabarty: System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1088-1094 (2002) |
10 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. J. Electronic Testing 18(2): 213-230 (2002) |
2001 | ||
9 | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test wrapper and test access mechanism co-optimization for system-on-chip. ITC 2001: 1023-1032 | |
8 | EE | Vikram Iyengar, Krishnendu Chakrabarty: Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. VTS 2001: 368-374 |
2000 | ||
7 | Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara: Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. PDPTA 2000 | |
6 | EE | Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar: Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. IEEE Trans. VLSI Syst. 8(5): 633-636 (2000) |
5 | EE | Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick: A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. J. Electronic Testing 16(1-2): 13-27 (2000) |
1999 | ||
4 | EE | Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar: Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. VTS 1999: 22-27 |
3 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray: Deterministic Built-in Pattern Generation for Sequential Circuits. J. Electronic Testing 15(1-2): 97-114 (1999) |
1998 | ||
2 | EE | Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray: Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. VTS 1998: 418-423 |
1997 | ||
1 | EE | Vikram Iyengar, Krishnendu Chakrabarty: An Efficient Finite-State Machine Implementation of Huffman Decoders. Inf. Process. Lett. 64(6): 271-275 (1997) |