Vikram Iyengar

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37EESudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar: AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ASP-DAC 2007: 823-828
36EEVikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah: Variation-aware performance verification using at-speed structural test and statistical timing. ICCAD 2007: 405-412
35EEVikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland: An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. VTS 2007: 173-178
34EEVikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich: Performance verification of high-performance ASICs using at-speed structural test. ACM Great Lakes Symposium on VLSI 2006: 247-252
33EEVikram Iyengar, Gary Grise, Mark Taylor: A flexible and scalable methodology for GHz-speed structural test. DAC 2006: 314-319
32EEChunsheng Liu, Vikram Iyengar: Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. DATE 2006: 652-657
31EEChunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan: Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. VTS 2006: 46-51
30EEVikram Iyengar, Phil Nigh: Defect-Oriented Test for Ultra-Low DPM. Asian Test Symposium 2005: 455
29EEChunsheng Liu, Kugesh Veeraraghavant, Vikram Iyengar: Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems. DFT 2005: 552-562
28EEChunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota: Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. VTS 2005: 349-354
27EEKrishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski: Test planning for modular testing of hierarchical SOCs. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 435-448 (2005)
26EEAnuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty: SOC test planning using virtual test access architectures. IEEE Trans. VLSI Syst. 12(12): 1263-1276 (2004)
25EEAnuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty: Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. DAC 2003: 738-743
24EEVikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty: A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. DATE 2003: 11188-11190
23EEVikram Iyengar, Anshuman Chandra: A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. DFT 2003: 511-518
22EEVikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar: Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. VTS 2003: 299-312
21EEVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. IEEE Trans. Computers 52(12): 1619-1632 (2003)
20EEVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Efficient test access mechanism optimization for system-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 635-643 (2003)
19EEVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. Asian Test Symposium 2002: 320-
18EEVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. DAC 2002: 685-690
17EEVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Efficient Wrapper/TAM Co-Optimization for Large SOCs. DATE 2002: 491-498
16EEVikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC 2002: 1159-1168
15EEErik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty: A Set of Benchmarks fo Modular Testing of SOCs. ITC 2002: 519-528
14EESandeep Koranne, Vikram Iyengar: On the Use of k-tuples for SoC Test Schedule Representation. ITC 2002: 539-548
13EEVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. VTS 2002: 253-258
12EEVikram Iyengar, Krishnendu Chakrabarty: Test Bus Sizing for System-on-a-Chip. IEEE Trans. Computers 51(5): 449-459 (2002)
11EEVikram Iyengar, Krishnendu Chakrabarty: System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1088-1094 (2002)
10EEVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. J. Electronic Testing 18(2): 213-230 (2002)
9 Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test wrapper and test access mechanism co-optimization for system-on-chip. ITC 2001: 1023-1032
8EEVikram Iyengar, Krishnendu Chakrabarty: Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. VTS 2001: 368-374
7 Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara: Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. PDPTA 2000
6EEKrishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar: Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. IEEE Trans. VLSI Syst. 8(5): 633-636 (2000)
5EETa-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick: A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. J. Electronic Testing 16(1-2): 13-27 (2000)
4EEKrishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar: Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. VTS 1999: 22-27
3EEVikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray: Deterministic Built-in Pattern Generation for Sequential Circuits. J. Electronic Testing 15(1-2): 97-114 (1999)
2EEVikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray: Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. VTS 1998: 418-423
1EEVikram Iyengar, Krishnendu Chakrabarty: An Efficient Finite-State Machine Implementation of Huffman Decoders. Inf. Process. Lett. 64(6): 271-275 (1997)

Coauthor Index

1Theo Anemikos [34]
2Sudarshan Bahukudumbi [37]
3Bob Bassett [34]
4Krishnendu Chakrabarty [1] [2] [3] [4] [6] [7] [8] [9] [10] [11] [12] [13] [15] [16] [17] [18] [19] [20] [21] [22] [24] [25] [26] [27] [37]
5Anshuman Chandra [23] [24]
6Ta-Chung Chang [5]
7Érika F. Cota [28]
8Hiroshi Date [7]
9Mike Degregorio [34] [35]
10Rudy Farmer [34]
11Andrew Ferko [35]
12Sandeep Kumar Goel [16]
13Gary Grise [33] [34] [35]
14Peter A. Habitz [36]
15Mark Johnson [34]
16Sandeep Koranne [14]
17Mark D. Krasniewski [22] [25] [27]
18Gopind N. Kumar [22]
19David E. Lackey [35] [36]
20Chunsheng Liu [28] [29] [31] [32]
21Erik Jan Marinissen [9] [10] [13] [15] [16] [17] [18] [19] [20] [21]
22Brian T. Murray [2] [3] [4] [6]
23Phil Nigh [30]
24Steven F. Oakland [35]
25Sule Ozev [37]
26Kenneth Pichamuthu [35]
27Dhiraj K. Pradhan [31]
28Elizabeth M. Rudnick [5]
29Sharon Schweizer [24]
30Anuja Sehgal [25] [26]
31Jiangfan Shi [28]
32Phil Stevens [34]
33Makoto Sugihara [7]
34Mark Taylor [33] [34] [35]
35Kugesh Veeraraghavant [29]
36Subbayyan Venkatesan [36]
37Chandu Visweswariah [36]
38Frank Woytowich [34] [35]
39Jinjun Xiong [36]
40Vladimir Zolotov [36]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)