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Laurent Fesquet

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2008
24EESumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98
23EEPhilippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks CoRR abs/0809.3942: (2008)
2007
22EEKatell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione: Asynchronous online-monitoring of logical and temporal assertions. FDL 2007: 286-290
21 Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22
20EEN. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic CoRR abs/0710.4711: (2007)
2006
19EEKatell Morin-Allory, Laurent Fesquet, Dominique Borrione: Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping 2006: 98-102
18EELaurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin: State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC 2006: 12-17
2005
17EEN. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic. DATE 2005: 32-33
16EED. Borionne, M. Liu, P. Ostier, Laurent Fesquet: PSL-based online monitoring of digital systems. FDL 2005: 465-479
15 Laurent Fesquet, Marc Renaudin: A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL 2005: 293-298
14 Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin: GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304
13 Laurent Fesquet, Jerome Quartana, Marc Renaudin: Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112
12EEJerome Quartana, Laurent Fesquet, Marc Renaudin: Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207
11EEBertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin: Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC 2005: 55-69
2004
10EEF. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin: Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC 2004: 198-206
2003
9EEEmmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin: A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC 2003: 196-205
2002
8EEJean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090
7EEQuoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland: Implementing Asynchronous Circuits on LUT Based FPGAs. FPL 2002: 36-46
6 Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin: Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196
5EEMohammed Es Salhiene, Laurent Fesquet, Marc Renaudin: Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS 2002: 390-399
4EEEmmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard: Low-Power Asynchronous A/D Conversion. PATMOS 2002: 81-91
2001
3 Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324
1999
2EEWissam Hlayhel, Jacques Collet, Laurent Fesquet: Implementing Snoop-Coherence Protocol for Future SMP Architectures. Euro-Par 1999: 745-752
1998
1EEWissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Collet: Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. IEEE PACT 1998: 22-29

Coauthor Index

1F. Aeschlimann [10]
2Emmanuel Allier [4] [9] [10]
3Arnaud Baixas [14]
4Taha Beyrouthy [21] [23] [24]
5D. Borionne [16]
6Dominique Borrione [19] [22]
7Vivian Brégier [11]
8Sumanta Chaudhuri [21] [23] [24]
9Jacques Collet [1] [2]
10Jean-Luc Danger [23] [24]
11H. Dubreuil [17] [20]
12Anh Vu Dihn Duc [6]
13Bertrand Folco [11] [18]
14Sylvain Guilley [21] [23] [24]
15Wissam Hlayhel [1] [2]
16Quoc Thai Ho [7]
17Philippe Hoogvorst [21] [23] [24]
18N. Huot [17] [20]
19Daniel Litaize [1]
20M. Liu [16]
21Katell Morin-Allory [19] [22]
22P. Ostier [16]
23Jerome Quartana [3] [8] [12] [13] [14]
24Alin Razafindraibe [21] [24]
25Salim Renane [14]
26Marc Renaudin [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [17] [18] [20] [24]
27Jean-Baptiste Rigaud [3] [7] [8]
28Robin Rolland [7]
29Benjamin Roustan [22]
30Mohammed Es Salhiene [5]
31Gilles Sicard [4] [9]
32M. Steiner [18]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)