2008 |
24 | EE | Sumanta Chaudhuri,
Sylvain Guilley,
Philippe Hoogvorst,
Jean-Luc Danger,
Taha Beyrouthy,
Alin Razafindraibe,
Laurent Fesquet,
Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage.
ARC 2008: 87-98 |
23 | EE | Philippe Hoogvorst,
Sylvain Guilley,
Sumanta Chaudhuri,
Jean-Luc Danger,
Taha Beyrouthy,
Laurent Fesquet:
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks
CoRR abs/0809.3942: (2008) |
2007 |
22 | EE | Katell Morin-Allory,
Laurent Fesquet,
Benjamin Roustan,
Dominique Borrione:
Asynchronous online-monitoring of logical and temporal assertions.
FDL 2007: 286-290 |
21 | | Philippe Hoogvorst,
Sylvain Guilley,
Sumanta Chaudhuri,
Alin Razafindraibe,
Taha Beyrouthy,
Laurent Fesquet:
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA.
ReCoSoC 2007: 15-22 |
20 | EE | N. Huot,
H. Dubreuil,
Laurent Fesquet,
Marc Renaudin:
FPGA Architecture for Multi-Style Asynchronous Logic
CoRR abs/0710.4711: (2007) |
2006 |
19 | EE | Katell Morin-Allory,
Laurent Fesquet,
Dominique Borrione:
Asynchronous Assertion Monitors for multi-Clock Domain System Verification.
IEEE International Workshop on Rapid System Prototyping 2006: 98-102 |
18 | EE | Laurent Fesquet,
Bertrand Folco,
M. Steiner,
Marc Renaudin:
State-holding in Look-Up Tables: application to asynchronous logic.
VLSI-SoC 2006: 12-17 |
2005 |
17 | EE | N. Huot,
H. Dubreuil,
Laurent Fesquet,
Marc Renaudin:
FPGA Architecture for Multi-Style Asynchronous Logic.
DATE 2005: 32-33 |
16 | EE | D. Borionne,
M. Liu,
P. Ostier,
Laurent Fesquet:
PSL-based online monitoring of digital systems.
FDL 2005: 465-479 |
15 | | Laurent Fesquet,
Marc Renaudin:
A Programmable Logic Architecture for Prototyping Clockless Circuits.
FPL 2005: 293-298 |
14 | | Jerome Quartana,
Salim Renane,
Arnaud Baixas,
Laurent Fesquet,
Marc Renaudin:
GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips.
FPL 2005: 299-304 |
13 | | Laurent Fesquet,
Jerome Quartana,
Marc Renaudin:
Asynchronous Systems on Programmable Logic.
ReCoSoC 2005: 105-112 |
12 | EE | Jerome Quartana,
Laurent Fesquet,
Marc Renaudin:
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.
VLSI-SoC 2005: 195-207 |
11 | EE | Bertrand Folco,
Vivian Brégier,
Laurent Fesquet,
Marc Renaudin:
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.
VLSI-SoC 2005: 55-69 |
2004 |
10 | EE | F. Aeschlimann,
Emmanuel Allier,
Laurent Fesquet,
Marc Renaudin:
Asynchronous FIR Filters: Towards a New Digital Processing Chain.
ASYNC 2004: 198-206 |
2003 |
9 | EE | Emmanuel Allier,
Gilles Sicard,
Laurent Fesquet,
Marc Renaudin:
A New Class of Asynchronous A/D Converters Based on Time Quantization.
ASYNC 2003: 196-205 |
2002 |
8 | EE | Jean-Baptiste Rigaud,
Laurent Fesquet,
Marc Renaudin,
Jerome Quartana:
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems.
DATE 2002: 1090 |
7 | EE | Quoc Thai Ho,
Jean-Baptiste Rigaud,
Laurent Fesquet,
Marc Renaudin,
Robin Rolland:
Implementing Asynchronous Circuits on LUT Based FPGAs.
FPL 2002: 36-46 |
6 | | Anh Vu Dihn Duc,
Laurent Fesquet,
Marc Renaudin:
Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net.
IWLS 2002: 191-196 |
5 | EE | Mohammed Es Salhiene,
Laurent Fesquet,
Marc Renaudin:
Dynamic Voltage Scheduling for Real Time Asynchronous Systems.
PATMOS 2002: 390-399 |
4 | EE | Emmanuel Allier,
Laurent Fesquet,
Marc Renaudin,
Gilles Sicard:
Low-Power Asynchronous A/D Conversion.
PATMOS 2002: 81-91 |
2001 |
3 | | Jean-Baptiste Rigaud,
Jerome Quartana,
Laurent Fesquet,
Marc Renaudin:
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.
VLSI-SOC 2001: 313-324 |
1999 |
2 | EE | Wissam Hlayhel,
Jacques Collet,
Laurent Fesquet:
Implementing Snoop-Coherence Protocol for Future SMP Architectures.
Euro-Par 1999: 745-752 |
1998 |
1 | EE | Wissam Hlayhel,
Daniel Litaize,
Laurent Fesquet,
Jacques Collet:
Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures.
IEEE PACT 1998: 22-29 |