| 2008 |
|---|
| 103 | EE | Pouria Bastani,
Nicholas Callegari,
Li-C. Wang,
Magdy S. Abadir:
Statistical diagnosis of unmodeled systematic timing effects.
DAC 2008: 355-360 |
| 102 | EE | Alper Sen,
Vinit Ogale,
Magdy S. Abadir:
Predictive runtime verification of multi-processor SoCs in SystemC.
DAC 2008: 948-953 |
| 101 | EE | Aseem Gupta,
Nikil D. Dutt,
Fadi J. Kurdahi,
Kamal S. Khouri,
Magdy S. Abadir:
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.
ISQED 2008: 470-475 |
| 100 | EE | Jayanta Bhadra,
Ekaterina Trofimova,
Magdy S. Abadir:
Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications.
IEEE Trans. VLSI Syst. 16(4): 388-396 (2008) |
| 2007 |
|---|
| 99 | | Magdy S. Abadir,
Li-C. Wang,
Jayanta Bhadra:
Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA
IEEE Computer Society 2007 |
| 98 | EE | Aseem Gupta,
Nikil D. Dutt,
Fadi J. Kurdahi,
Kamal S. Khouri,
Magdy S. Abadir:
LEAF: A System Level Leakage-Aware Floorplanner for SoCs.
ASP-DAC 2007: 274-279 |
| 97 | EE | Li-C. Wang,
Pouria Bastani,
Magdy S. Abadir:
Design-Silicon Timing Correlation A Data Mining Perspective.
DAC 2007: 384-389 |
| 96 | EE | Hratch Mangassarian,
Andreas G. Veneris,
Sean Safarpour,
Farid N. Najm,
Magdy S. Abadir:
Maximum circuit activity estimation using pseudo-boolean satisfiability.
DATE 2007: 1538-1543 |
| 95 | EE | Aseem Gupta,
Nikil D. Dutt,
Fadi J. Kurdahi,
Kamal S. Khouri,
Magdy S. Abadir:
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.
VLSI Design 2007: 559-564 |
| 94 | EE | Jayanta Bhadra,
Magdy S. Abadir,
Li-C. Wang:
Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques.
IEEE Design & Test of Computers 24(2): 110-111 (2007) |
| 93 | EE | Jayanta Bhadra,
Magdy S. Abadir,
Li-C. Wang,
Sandip Ray:
A Survey of Hybrid Techniques for Functional Verification.
IEEE Design & Test of Computers 24(2): 112-122 (2007) |
| 2006 |
|---|
| 92 | | Magdy S. Abadir,
Li-C. Wang,
Jayanta Bhadra:
Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA
IEEE Computer Society 2006 |
| 91 | EE | Aseem Gupta,
Nikil D. Dutt,
Fadi J. Kurdahi,
Kamal S. Khouri,
Magdy S. Abadir:
Floorplan driven leakage power aware IP-based SoC design space exploration.
CODES+ISSS 2006: 118-123 |
| 90 | EE | Benjamin N. Lee,
Li-C. Wang,
Magdy S. Abadir:
Refined statistical static timing analysis through.
DAC 2006: 149-154 |
| 89 | EE | Onur Guzey,
Charles H.-P. Wen,
Li-C. Wang,
Tao Feng,
Hillel Miller,
Magdy S. Abadir:
Extracting a Simplified View of Design Functionality Based on Vector Simulation.
Haifa Verification Conference 2006: 34-49 |
| 88 | EE | Magdy S. Abadir:
Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs.
IOLTS 2006: 81 |
| 87 | EE | Heon-Mo Koo,
Prabhat Mishra,
Jayanta Bhadra,
Magdy S. Abadir:
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.
MTV 2006: 33-36 |
| 2005 |
|---|
| 86 | | Magdy S. Abadir,
Li-C. Wang:
Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA
IEEE Computer Society 2005 |
| 85 | EE | Jiang Brandon Liu,
Magdy S. Abadir,
Andreas G. Veneris,
Sean Safarpour:
Diagnosing multiple transition faults in the absence of timing information.
ACM Great Lakes Symposium on VLSI 2005: 193-196 |
| 84 | EE | Dennis Wassung,
Yervant Zorian,
Magdy S. Abadir,
Mark Bapst,
Colin Harris:
Choosing flows and methodologies for SoC design.
DAC 2005: 167 |
| 83 | | Moayad Fahim Ali,
Sean Safarpour,
Andreas G. Veneris,
Magdy S. Abadir,
Rolf Drechsler:
Post-verification debugging of hierarchical designs.
ICCAD 2005: 871-876 |
| 82 | EE | Jayanta Bhadra,
Magdy S. Abadir,
David Burgess,
Ekaterina Trofimova:
Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.
MTV 2005: 111-118 |
| 81 | EE | Brian Kahne,
Magdy S. Abadir:
Retiming Verification Using Sequential Equivalence Checking.
MTV 2005: 138-142 |
| 80 | EE | Moayad Fahim Ali,
Sean Safarpour,
Andreas G. Veneris,
Magdy S. Abadir,
Rolf Drechsler:
Post-Verification Debugging of Hierarchical Designs.
MTV 2005: 42-47 |
| 79 | EE | Dhiraj K. Pradhan,
Magdy S. Abadir,
Mauricio Varea:
Recent Advances in Verification, Equivalence Checking and SAT-Solvers.
VLSI Design 2005: 14 |
| 78 | EE | Benjamin N. Lee,
Li-C. Wang,
Magdy S. Abadir:
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects.
VTS 2005: 153-160 |
| 77 | EE | Prabhat Mishra,
Nikil D. Dutt,
Narayanan Krishnamurthy,
Magdy S. Abadir:
A methodology for validation of microprocessors using symbolic simulation.
IJES 1(1/2): 14-22 (2005) |
| 76 | EE | Andreas G. Veneris,
Robert Chang,
Magdy S. Abadir,
Sep Seyedi:
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.
J. Electronic Testing 21(5): 495-502 (2005) |
| 2004 |
|---|
| 75 | EE | Mahesh Mamidipaka,
Kamal S. Khouri,
Nikil D. Dutt,
Magdy S. Abadir:
Analytical models for leakage power estimation of memory array structures.
CODES+ISSS 2004: 146-151 |
| 74 | EE | Li-C. Wang,
T. M. Mak,
Kwang-Ting Cheng,
Magdy S. Abadir:
On path-based learning and its applications in delay test and diagnosis.
DAC 2004: 492-497 |
| 73 | EE | Moayad Fahim Ali,
Andreas G. Veneris,
Alexander Smith,
Sean Safarpour,
Rolf Drechsler,
Magdy S. Abadir:
Debugging sequential circuits using Boolean satisfiability.
ICCAD 2004: 204-209 |
| 72 | | Andreas G. Veneris,
Robert Chang,
Magdy S. Abadir,
Mandana Amiri:
Fault equivalence and diagnostic test generation using ATPG.
ISCAS (5) 2004: 221-224 |
| 71 | EE | Jing Zeng,
Magdy S. Abadir,
A. Kolhatkar,
G. Vandling,
Li-C. Wang,
Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
ITC 2004: 31-37 |
| 70 | EE | Jing Zeng,
Magdy S. Abadir,
G. Vandling,
Li-C. Wang,
S. Karako,
Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
MTV 2004: 103-109 |
| 69 | EE | Moayad Fahim Ali,
Andreas G. Veneris,
Sean Safarpour,
Magdy S. Abadir,
Freescale Semiconductor,
Rolf Drechsler,
Alexander Smith:
Debugging Sequential Circuits Using Boolean Satisfiability.
MTV 2004: 44-49 |
| 68 | EE | M. Moiz Khan,
Spyros Tragoudas,
Magdy S. Abadir,
Jiang Brandon Liu:
Identification of Gates for Covering all Critical Paths.
MTV 2004: 92-96 |
| 67 | EE | Narayanan Krishnamurthy,
Jayanta Bhadra,
Magdy S. Abadir,
Jacob A. Abraham:
Towards The Complete Elimination of Gate/Switch Level Simulations.
VLSI Design 2004: 115- |
| 66 | EE | Prabhat Mishra,
Nikil Dutt,
Narayanan Krishnamurthy,
Magdy S. Abadir:
A Top-Down Methodology for Microprocessor Validation.
IEEE Design & Test of Computers 21(2): 122-131 (2004) |
| 65 | EE | Magdy S. Abadir,
Li-C. Wang:
Guest Editors' Introduction: The Verification and Test of Complex Digital ICs.
IEEE Design & Test of Computers 21(2): 80-82 (2004) |
| 64 | EE | Jayanta Bhadra,
Narayanan Krishnamurthy,
Magdy S. Abadir:
Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation.
IEEE Design & Test of Computers 21(6): 494-502 (2004) |
| 63 | EE | Mahesh Mamidipaka,
Kamal S. Khouri,
Nikil D. Dutt,
Magdy S. Abadir:
IDAP: a tool for high-level power estimation of custom array structures.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1361-1369 (2004) |
| 2003 |
|---|
| 62 | EE | Magdy S. Abadir,
Jing Zeng,
Carol Pyron,
Juhong Zhu:
Automated Test Model Generation from Switch Level Custom Circuits.
Asian Test Symposium 2003: 184-189 |
| 61 | EE | Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng,
Jing-Jia Liou,
Magdy S. Abadir:
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step.
DATE 2003: 10328-10335 |
| 60 | EE | Mahesh Mamidipaka,
Kamal S. Khouri,
Nikil D. Dutt,
Magdy S. Abadir:
IDAP: A Tool for High Level Power Estimation of Custom Array Structures.
ICCAD 2003: 113-119 |
| 59 | EE | Li-C. Wang,
Angela Krstic,
Leonard Lee,
Kwang-Ting Cheng,
M. Ray Mercer,
Thomas W. Williams,
Magdy S. Abadir:
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.
ITC 2003: 1041-1050 |
| 58 | EE | Jayanta Bhadra,
Narayanan Krishnamurthy,
Magdy S. Abadir:
A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits.
MTV 2003: 32-37 |
| 57 | EE | Magdy S. Abadir,
Juhong Zhu:
Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs.
VTS 2003: 22-30 |
| 56 | EE | Magdy S. Abadir,
Ken Albin,
John Havlicek,
Narayanan Krishnamurthy,
Andrew K. Martin:
Formal Verification Successes at Motorola.
Formal Methods in System Design 22(2): 117-123 (2003) |
| 2002 |
|---|
| 55 | EE | Jing Zeng,
Magdy S. Abadir,
Jacob A. Abraham:
False timing path identification using ATPG techniques and delay-based information.
DAC 2002: 562-565 |
| 54 | EE | Andreas G. Veneris,
Jiang Brandon Liu,
Mandana Amiri,
Magdy S. Abadir:
Incremental Diagnosis and Correction of Multiple Faults and Errors.
DATE 2002: 716-721 |
| 53 | EE | A. J. van de Goor,
Magdy S. Abadir,
Alan Carlin:
Minimal Test for Coupling Faults in Word-Oriented Memories.
DATE 2002: 944-948 |
| 52 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Tao Feng,
Li-C. Wang,
Kwang-Ting Cheng,
Magdy S. Abadir:
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.
ITC 2002: 203-212 |
| 51 | EE | Andreas G. Veneris,
Magdy S. Abadir,
Mandana Amiri:
Design Rewiring Using ATPG.
ITC 2002: 223-232 |
| 50 | EE | Li-C. Wang,
Magdy S. Abadir,
Juhong Zhu:
On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.
ITC 2002: 398-406 |
| 49 | EE | Narayanan Krishnamurthy,
Jayanta Bhadra,
Magdy S. Abadir,
Jacob A. Abraham:
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?
VTS 2002: 275-280 |
| 48 | EE | Andreas G. Veneris,
Magdy S. Abadir:
Design rewiring using ATPG.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1469-1479 (2002) |
| 2001 |
|---|
| 47 | EE | Andreas G. Veneris,
Magdy S. Abadir,
Ivor Ting:
Design rewiring based on diagnosis techniques.
ASP-DAC 2001: 479-484 |
| 46 | EE | Jayanta Bhadra,
Andrew K. Martin,
Jacob A. Abraham,
Magdy S. Abadir:
Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation.
CHARME 2001: 386-402 |
| 45 | EE | Jing Zeng,
Magdy S. Abadir,
Jayanta Bhadra,
Jacob A. Abraham:
Full chip false timing path identification: applications to the PowerPCTM microprocessors.
DATE 2001: 514-519 |
| 44 | EE | Mrinal Bose,
Elizabeth M. Rudnick,
Magdy S. Abadir:
Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.
IOLTW 2001: 65- |
| 43 | EE | Magdy S. Abadir,
Li-C. Wang:
Verification and Validation of Complex Digital Systems: An Industrial Perspective.
ISQED 2001: 11-12 |
| 42 | EE | Magdy S. Abadir,
Juhong Zhu,
Li-C. Wang:
Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor.
VTS 2001: 252-259 |
| 41 | EE | Magdy S. Abadir,
Scott Davidson,
Vijay Nagasamy,
Dhiraj K. Pradhan,
Prab Varma:
ATPG for Design Errors-Is It Possible?
VTS 2001: 283-285 |
| 40 | EE | Narayanan Krishnamurthy,
Magdy S. Abadir,
Andrew K. Martin,
Jacob A. Abraham:
Design and Development Paradigm for Industrial Formal Verification CAD Tools.
IEEE Design & Test of Computers 18(4): 26-35 (2001) |
| 39 | EE | Jay Bedsole,
Rajesh Raina,
Al Crouch,
Magdy S. Abadir:
Very Low Cost Testers: Opportunities and Challenges.
IEEE Design & Test of Computers 18(5): 60-69 (2001) |
| 2000 |
|---|
| 38 | EE | Narayanan Krishnamurthy,
Andrew K. Martin,
Magdy S. Abadir,
Jacob A. Abraham:
Validation of PowerPC(tm) Custom Memories using Symbolic Simulation.
VTS 2000: 9-14 |
| 37 | | Magdy S. Abadir,
Sumit Dasgupta:
Guest Editors' Introduction: Microprocessor Test and Verification.
IEEE Design & Test of Computers 17(4): 4-5 (2000) |
| 36 | EE | Narayanan Krishnamurthy,
Andrew K. Martin,
Magdy S. Abadir,
Jacob A. Abraham:
Validating PowerPC Microprocessor Custom Memories.
IEEE Design & Test of Computers 17(4): 61-76 (2000) |
| 35 | EE | Li-C. Wang,
Magdy S. Abadir:
On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors.
J. Electronic Testing 16(1-2): 121-130 (2000) |
| 34 | EE | Wen Ching Wu,
Chung-Len Lee,
Ming Shae Wu,
Jwu E. Chen,
Magdy S. Abadir:
Oscillation Ring Delay Test for High Performance Microprocessors.
J. Electronic Testing 16(1-2): 147-155 (2000) |
| 33 | EE | Magdy S. Abadir:
Guest Editorial.
J. Electronic Testing 16(1-2): 9-10 (2000) |
| 1999 |
|---|
| 32 | | Magdy S. Abadir,
Rajesh Raina:
Design-for-test methodology for Motorola PowerPC microprocessors.
ITC 1999: 810-819 |
| 31 | | Li-C. Wang,
Magdy S. Abadir:
Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors.
ITC 1999: 830-838 |
| 30 | EE | Li-C. Wang,
Magdy S. Abadir:
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays.
J. Electronic Testing 15(1-2): 191-205 (1999) |
| 1998 |
|---|
| 29 | EE | Li-C. Wang,
Magdy S. Abadir,
Nari Krishnamurthy:
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation.
DAC 1998: 534-537 |
| 28 | EE | Li-C. Wang,
Magdy S. Abadir,
Jing Zeng:
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.
DATE 1998: 273-277 |
| 27 | EE | Arun Chandra,
Li-C. Wang,
Magdy S. Abadir:
Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors.
Great Lakes Symposium on VLSI 1998: 362-367 |
| 26 | EE | Li-C. Wang,
Magdy S. Abadir,
Jing Zeng:
On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays.
VTS 1998: 260-265 |
| 25 | EE | Li-C. Wang,
Magdy S. Abadir,
Jing Zeng:
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.
ACM Trans. Design Autom. Electr. Syst. 3(4): 524-532 (1998) |
| 24 | EE | Li-C. Wang,
Magdy S. Abadir:
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.
J. Electronic Testing 13(2): 121-135 (1998) |
| 1997 |
|---|
| 23 | EE | Manish Pandey,
Richard Raimi,
Randal E. Bryant,
Magdy S. Abadir:
Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation.
DAC 1997: 167-172 |
| 22 | | Li-C. Wang,
Magdy S. Abadir:
A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays.
ITC 1997: 954-963 |
| 21 | EE | Magdy S. Abadir,
Jacob A. Abraham,
H. Hao,
C. Hunter,
Wayne M. Needham,
Ron G. Walther:
Microprocessor Test and Validation: Any New Avenues?
VTS 1997: 458-464 |
| 20 | | Tony Ambler,
Magdy S. Abadir:
Design and Test Economics-An Extra Dimension.
IEEE Design & Test of Computers 14(3): 15-16 (1997) |
| 19 | EE | Magdy S. Abadir,
Rohit Kapur:
Cost-Driven Ranking of Memory Elements for Partial Intrusion.
IEEE Design & Test of Computers 14(3): 45-50 (1997) |
| 18 | | Jawahar Jain,
James R. Bitner,
Magdy S. Abadir,
Jacob A. Abraham,
Donald S. Fussell:
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions.
IEEE Trans. Computers 46(11): 1230-1245 (1997) |
| 17 | EE | Cynthia F. Murphy,
Magdy S. Abadir,
Peter Sandborn:
Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die.
J. Electronic Testing 10(1-2): 151-166 (1997) |
| 1996 |
|---|
| 16 | | Neeta Ganguly,
Magdy S. Abadir,
Manish Pandey:
PowerPCTM Array Verification Methodology using Formal Techniques.
ITC 1996: 857-864 |
| 1994 |
|---|
| 15 | | James R. Bitner,
Jawahar Jain,
Magdy S. Abadir,
Jacob A. Abraham,
Donald S. Fussell:
Efficient Algorithmic Circuit Verification Using Indexed BDDs.
FTCS 1994: 266-275 |
| 14 | EE | Magdy S. Abadir,
Ashish R. Parikh,
Linda Bal,
Peter Sandborn,
Ken Drake:
Analyzing Multichip Module Testing Strategies.
IEEE Design & Test of Computers 11(1): 40-52 (1994) |
| 13 | EE | Magdy S. Abadir,
Tony Ambler:
Introduction.
J. Electronic Testing 5(2-3): 129-130 (1994) |
| 12 | EE | Magdy S. Abadir,
Ashish Parikh,
Linda Bal,
Peter Sandborn,
Cynthia Murphy:
High Level Test Economics Advisor (Hi-TEA).
J. Electronic Testing 5(2-3): 195-206 (1994) |
| 11 | EE | Peter Sandborn,
Rajarshi Ghosh,
Ken Drake,
Magdy S. Abadir,
Linda Bal,
Ashish Parikh:
Multichip systems trade-off analysis tool.
J. Electronic Testing 5(2-3): 207-218 (1994) |
| 1993 |
|---|
| 10 | | Praveen Vishakantaiah,
Thomas Thomas,
Jacob A. Abraham,
Magdy S. Abadir:
AMBIANT: Automatic Generation of Behavioral Modifications for Testability.
ICCD 1993: 63-66 |
| 1992 |
|---|
| 9 | EE | Praveen Vishakantaiah,
Jacob A. Abraham,
Magdy S. Abadir:
Automatic Test Knowledge Extraction from VHDL (ATKET).
DAC 1992: 273-278 |
| 1991 |
|---|
| 8 | | Magdy S. Abadir,
Joe Newman,
Desmond D'Souza,
Steve Spencer:
Partitioning Hierarchical Designs for Testability.
ITC 1991: 174-183 |
| 1990 |
|---|
| 7 | EE | Magdy S. Abadir,
Jack Ferguson:
An improved layout verification algorithm (LAVA).
EURO-DAC 1990: 391-395 |
| 1988 |
|---|
| 6 | EE | Magdy S. Abadir,
Jack Ferguson,
Tom E. Kirkland:
Logic design verification via test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 138-148 (1988) |
| 1986 |
|---|
| 5 | | Magdy S. Abadir,
Melvin A. Breuer:
Scan Path with Look Ahead Shifting (SPLASH).
ITC 1986: 696-704 |
| 4 | | Magdy S. Abadir,
Melvin A. Breuer:
Test Schedules for VLSI Circuits Having Built-In Test Hardware.
IEEE Trans. Computers 35(4): 361-367 (1986) |
| 3 | | Magdy S. Abadir,
Hassan K. Reghbati:
Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams.
IEEE Trans. Computers 35(4): 375-379 (1986) |
| 1985 |
|---|
| 2 | | Magdy S. Abadir,
Hassan K. Reghbati:
Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams.
ITC 1985: 483-492 |
| 1983 |
|---|
| 1 | | Magdy S. Abadir,
Hassan K. Reghbati:
Functional Testing of Semiconductor Random Access Memories.
ACM Comput. Surv. 15(3): 175-198 (1983) |
