| 2006 |
|---|
| 9 | EE | Wei Zhang,
Yuh-Fang Tsai,
David Duarte,
Narayanan Vijaykrishnan,
Mahmut T. Kandemir,
Mary Jane Irwin:
Reducing dynamic and leakage energy in VLIW architectures.
ACM Trans. Embedded Comput. Syst. 5(1): 1-28 (2006) |
| 2003 |
|---|
| 8 | EE | Yuh-Fang Tsai,
David Duarte,
Narayanan Vijaykrishnan,
Mary Jane Irwin:
Implications of technology scaling on leakage reduction techniques.
DAC 2003: 187-190 |
| 7 | EE | Narayanan Vijaykrishnan,
Mahmut T. Kandemir,
Mary Jane Irwin,
Hyun Suk Kim,
Wu Ye,
David Duarte:
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework.
IEEE Trans. Computers 52(1): 59-76 (2003) |
| 2002 |
|---|
| 6 | EE | David Duarte,
Narayanan Vijaykrishnan,
Mary Jane Irwin:
A Complete Phase-Locked Loop Power Consumption Model.
DATE 2002: 1108 |
| 5 | EE | David Duarte,
Narayanan Vijaykrishnan,
Mary Jane Irwin,
Hyun Suk Kim,
G. McFarland:
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes.
ICCD 2002: 382-387 |
| 4 | EE | David Duarte,
Narayanan Vijaykrishnan,
Mary Jane Irwin:
Impact of Technology Scaling in the Clock System Power.
ISVLSI 2002: 59-64 |
| 3 | EE | David Duarte,
Yuh-Fang Tsai,
Narayanan Vijaykrishnan,
Mary Jane Irwin:
Evaluating Run-Time Techniques for Leakage Power Reduction.
VLSI Design 2002: 31-38 |
| 2001 |
|---|
| 2 | EE | Wei Zhang,
Narayanan Vijaykrishnan,
Mahmut T. Kandemir,
Mary Jane Irwin,
David Duarte,
Yuh-Fang Tsai:
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction.
MICRO 2001: 102-113 |
| 1 | EE | David Duarte,
Narayanan Vijaykrishnan,
Mary Jane Irwin,
Mahmut T. Kandemir:
Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks.
VLSI Design 2001: 248-253 |
