| 2002 |
|---|
| 9 | EE | Jin-Fu Li,
Hsin-Jung Huang,
Jeng-Bin Chen,
Chih-Pin Su,
Cheng-Wen Wu,
Chuang Cheng,
Shao-I Chen,
Chi-Yi Hwang,
Hsiao-Ping Lin:
A Hierarchical Test Scheme for System-On-Chip Designs.
DATE 2002: 486-490 |
| 8 | EE | Jin-Fu Li,
Hsin-Jung Huang,
Jeng-Bin Chen,
Chih-Pin Su,
Cheng-Wen Wu,
Chuang Cheng,
Shao-I Chen,
Chi-Yi Hwang,
Hsiao-Ping Lin:
A Hierarchical Test Methodology for Systems on Chip.
IEEE Micro 22(5): 69-81 (2002) |
| 1993 |
|---|
| 7 | EE | Chi-Yi Hwang,
Yung-Ching Hsieh,
Youn-Long Lin,
Yu-Chin Hsu:
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 410-424 (1993) |
| 1991 |
|---|
| 6 | EE | Min-Siang Lin,
Hourng-Wern Perng,
Chi-Yi Hwang,
Youn-Long Lin:
Channel Density Reduction by Routing Over The Cells.
DAC 1991: 120-125 |
| 5 | EE | Chi-Yi Hwang,
Yung-Ching Hsieh,
Youn-Long Lin,
Yu-Chin Hsu:
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation.
DAC 1991: 481-486 |
| 4 | EE | Min-Siang Lin,
Houng-Wern Perng,
Chi-Yi Hwang,
Youn-Long Lin:
Channel density reduction by routing over the cells.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1067-1071 (1991) |
| 3 | EE | Yung-Ching Hsieh,
Chi-Yi Hwang,
Youn-Long Lin,
Yu-Chin Hsu:
LiB: a CMOS cell compiler.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 994-1005 (1991) |
| 1990 |
|---|
| 2 | EE | Yung-Ching Hsieh,
Chi-Yi Hwang,
Youn-Long Lin,
Yu-Chin Hsu:
LiB: A Cell Layout Generator.
DAC 1990: 474-479 |
| 1 | EE | Chi-Yi Hwang,
Yung-Chin Hsieh,
Youn-Long Lin,
Yu-Chin Hsu:
A fast transistor-chaining algorithm for CMOS cell layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 781-786 (1990) |
