| 2008 |
|---|
| 126 | EE | Andrea Falletto,
Paolo Prinetto,
Gabriele Tiotto:
An Avatar-Based Italian Sign Language Visualization System.
eHealth 2008: 154-160 |
| 125 | EE | Alfredo Benso,
Alberto Bosio,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
March Test Generation Revealed.
IEEE Trans. Computers 57(12): 1704-1713 (2008) |
| 124 | EE | Alfredo Benso,
Stefano Di Carlo,
Paolo Prinetto,
Yervant Zorian:
IEEE Standard 1500 Compliance Verification for Embedded Cores.
IEEE Trans. VLSI Syst. 16(4): 397-407 (2008) |
| 2007 |
|---|
| 123 | EE | Mohammad Hosseinabady,
Mohammad Hossein Neishaburi,
Zainalabedin Navabi,
Alfredo Benso,
Stefano Di Carlo,
Paolo Prinetto,
Giorgio Di Natale:
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
IOLTS 2007: 205-206 |
| 2006 |
|---|
| 122 | EE | Alfredo Benso,
Alberto Bosio,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
Automatic march tests generations for static linked faults in SRAMs.
DATE 2006: 1258-1263 |
| 121 | | Alfredo Benso,
Alberto Bosio,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
DDECS 2006: 157-158 |
| 120 | EE | Alfredo Benso,
Alberto Bosio,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
Automatic March Tests Generation for Multi-Port SRAMs.
DELTA 2006: 385-392 |
| 119 | EE | Mohammad Hosseinabady,
Pejman Lotfi-Kamran,
Giorgio Di Natale,
Stefano Di Carlo,
Alfredo Benso,
Paolo Prinetto:
Single-Event Upset Analysis and Protection in High Speed Circuits.
European Test Symposium 2006: 29-34 |
| 118 | EE | Alfredo Benso,
Alberto Bosio,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
A 22n March Test for Realistic Static Linked Faults in SRAMs.
European Test Symposium 2006: 49-54 |
| 117 | EE | Mark D. Hill,
Jean-Luc Gaudiot,
Mary W. Hall,
Joe Marks,
Paolo Prinetto,
Donna Baglio:
A Wiki for discussing and promoting best practices in research.
Commun. ACM 49(9): 63-64 (2006) |
| 2005 |
|---|
| 116 | EE | Andrea Baldini,
Alfredo Benso,
Paolo Prinetto:
A Dependable Autonomic Computing Environment for Self-Testing of Complex Heterogeneous Systems.
Electr. Notes Theor. Comput. Sci. 116: 47-57 (2005) |
| 115 | EE | Liviu Miclea,
Szilárd Enyedi,
Paolo Prinetto,
Alfredo Benso:
Agent-based test and repair of distributed systems.
J. Embedded Computing 1(3): 405-414 (2005) |
| 114 | EE | Andrea Baldini,
Alfredo Benso,
Paolo Prinetto:
System-level functional testing from UML specifications in end-of-production industrial environments.
STTT 7(4): 326-340 (2005) |
| 2004 |
|---|
| 113 | EE | Marie-Lise Flottes,
Yves Bertrand,
L. Balado,
E. Lupon,
Anton Biasizzo,
Franc Novak,
Stefano Di Carlo,
Paolo Prinetto,
N. Pricopi,
Hans-Joachim Wunderlich:
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
DELTA 2004: 135-139 |
| 112 | EE | Liviu Miclea,
Szilárd Enyedi,
Gavril Toderean,
Alfredo Benso,
Paolo Prinetto:
Towards Microagent based DBIST/DBISR.
ITC 2004: 867-874 |
| 111 | | Paolo Prinetto,
Alfredo Benso:
Test Technology TC Newsletter.
IEEE Design & Test of Computers 21(2): 164-165 (2004) |
| 110 | EE | Paolo Prinetto:
Test Technology Technical Council Newsletter.
J. Electronic Testing 20(3): 221-225 (2004) |
| 2003 |
|---|
| 109 | EE | Fabrizio Bertuccelli,
Franco Bigongiari,
Andrea S. Brogna,
Giorgio Di Natale,
Paolo Prinetto,
Roberto Saletti:
Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool.
Asian Test Symposium 2003: 32-37 |
| 108 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
A Watchdog Processor to Detect Data and Control Flow Errors.
IOLTS 2003: 144-148 |
| 107 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto,
I. Solcia,
Luca Tagliaferri:
FAUST: FAUlt-injection Script-based Tool.
IOLTS 2003: 160 |
| 106 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto,
Luca Tagliaferri:
Data Critically Estimation In Software Applications.
ITC 2003: 802-810 |
| 105 | EE | Liviu Miclea,
Szilárd Enyedi,
Gavril Toderean,
Alfredo Benso,
Paolo Prinetto:
Agent Based DBIST/DBISR And Its Web/Wireless Management.
ITC 2003: 952-960 |
| 104 | EE | Yves Bertrand,
Marie-Lise Flottes,
L. Balado,
Joan Figueras,
Anton Biasizzo,
Franc Novak,
Stefano Di Carlo,
Paolo Prinetto,
N. Pricopi,
Hans-Joachim Wunderlich,
J.-P. Van der Heyden:
Test Engineering Education in Europe: the EuNICE-Test Project.
MSE 2003: 85-86 |
| 103 | | Andrea S. Brogna,
Franco Bigongiari,
Silvia Chiusano,
Paolo Prinetto,
Roberto Saletti:
Designing and Testing High Dependable Memories for Aerospace Applications.
VLSI-SOC 2003: 221- |
| 102 | EE | Andrea Baldini,
Paolo Prinetto,
Giovanni Denaro,
Mauro Pezzè:
Design for Testability for Highly Reconfigurable Component-Based Systems.
Electr. Notes Theor. Comput. Sci. 82(6): (2003) |
| 101 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
Online Self-Repair of FIR Filters.
IEEE Design & Test of Computers 20(3): 50-57 (2003) |
| 100 | EE | Alfredo Benso,
Stefano Di Carlo,
Paolo Prinetto,
Yervant Zorian:
A Hierarchical Infrastructure for SoC Test Management.
IEEE Design & Test of Computers 20(4): 32-39 (2003) |
| 2002 |
|---|
| 99 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
Specification and Design of a New Memory Fault Simulator.
Asian Test Symposium 2002: 92-97 |
| 98 | EE | Andrea Baldini,
Alfredo Benso,
Paolo Prinetto,
Sergio Mo,
Andrea Taddei:
Beyond UML to an End-of-Line Functional Test Engine.
DATE 2002: 499-505 |
| 97 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
An Optimal Algorithm for the Automatic Generation of March Tests.
DATE 2002: 938-943 |
| 96 | EE | Michel Renovell,
Penelope Faure,
Paolo Prinetto,
Yervant Zorian:
Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA.
DELTA 2002: 297-301 |
| 95 | EE | Silvia Chiusano,
Stefano Di Carlo,
Paolo Prinetto:
Automated Synthesis of SEU Tolerant Architectures from OO Descriptions.
IOLTW 2002: 26-31 |
| 94 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
Static Analysis of SEU Effects on Software Applications.
ITC 2002: 500-508 |
| 93 | EE | Andrea Baldini,
Alfredo Benso,
Paolo Prinetto,
Sergio Mo,
Andrea Taddei:
Efficient Design of System Test: A Layered Architecture.
ITC 2002: 930-939 |
| 92 | EE | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Giovanni Squillero:
Initializability analysis of synchronous sequential circuits.
ACM Trans. Design Autom. Electr. Syst. 7(2): 249-264 (2002) |
| 91 | EE | Alfredo Benso,
Silvia Chiusano,
Paolo Prinetto:
DFT and BIST of a Multichip Module for High-Energy Physics Experiments.
IEEE Design & Test of Computers 19(3): 94-105 (2002) |
| 2001 |
|---|
| 90 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
Memory Read Faults: Taxonomy and Automatic Test Generation.
Asian Test Symposium 2001: 157-163 |
| 89 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto,
Luca Tagliaferri:
Control-Flow Checking via Regular Expressions.
Asian Test Symposium 2001: 299-303 |
| 88 | EE | Silvia Chiusano,
Stefano Di Carlo,
Paolo Prinetto,
Hans-Joachim Wunderlich:
On applying the set covering model to reseeding.
DATE 2001: 156-161 |
| 87 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto:
SEU effect analysis in an open-source router via a distributed fault injection environment.
DATE 2001: 219-225 |
| 86 | EE | Yervant Zorian,
Paolo Prinetto,
João Paulo Teixeira,
Isabel C. Teixeira,
Carlos Eduardo Pereira,
Octávio Páscoa Dias,
Jorge Semião,
Peter Muhmenthaler,
W. Radermacher:
Embedded tutorial: TRP: integrating embedded test and ATE.
DATE 2001: 34-37 |
| 85 | EE | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Luca Tagliaferri,
Paolo Prinetto:
Validation of a Software Dependability Tool via Fault Injection Experiments.
IOLTW 2001: 3-8 |
| 84 | | Silvia Chiusano,
Giorgio Di Natale,
Paolo Prinetto,
Franco Bigongiari:
GRAAL: a tool for highly dependable SRAMs generation.
ITC 2001: 250-257 |
| 83 | | Andrea Baldini,
Alfredo Benso,
Paolo Prinetto,
Sergio Mo,
Andrea Taddei:
Towards a unified test process: from UML to end-of-line functional test.
ITC 2001: 600-608 |
| 82 | EE | Alfredo Benso,
Silvia Chiusano,
Giorgio Di Natale,
Paolo Prinetto,
Monica Lobetti Bodoni:
Online and Offline BIST in IP-Core Design.
IEEE Design & Test of Computers 18(5): 92-99 (2001) |
| 81 | EE | Alfredo Benso,
Silvia Chiusano,
Paolo Prinetto:
A Self-Repairing Execution Unit for Microprogrammed Processors.
IEEE Micro 21(5): 16-22 (2001) |
| 80 | EE | Paolo Prinetto,
Joan Figueras:
Guest Editorial.
J. Electronic Testing 17(3-4): 207 (2001) |
| 2000 |
|---|
| 79 | EE | Silvia Cataldo,
Silvia Chiusano,
Paolo Prinetto,
Hans-Joachim Wunderlich:
Optimal Hardware Pattern Generation for Functional BIST.
DATE 2000: 292-297 |
| 78 | EE | Alfredo Benso,
Silvia Chiusano,
Paolo Prinetto,
P. Simonotti,
G. Ugo:
Self-Repairing in a Micro-Programmed Processor for Dependable Applications.
DFT 2000: 231-239 |
| 77 | EE | Andrea Baldini,
Alfredo Benso,
Silvia Chiusano,
Paolo Prinetto:
'BOND': An Interposition Agents Based Fault Injector for Windows NT.
DFT 2000: 387-395 |
| 76 | EE | Alfredo Benso,
Silvia Chiusano,
Paolo Prinetto,
Luca Tagliaferri:
A C/C++ Source-to-Source Compiler for Dependable Applications.
DSN 2000: 71- |
| 75 | EE | Alfredo Benso,
Stefano Martinetto,
Paolo Prinetto,
Riccardo Mariani:
An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications.
ICCD 2000: 537-538 |
| 74 | EE | Alfredo Benso,
Stefano Di Carlo,
Silvia Chiusano,
Paolo Prinetto,
Fabio Ricciato,
Monica Lobetti Bodoni,
Maurizio Spadari:
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs.
ICCD 2000: 539-540 |
| 73 | EE | Alfredo Benso,
Silvia Chiusano,
Giorgio Di Natale,
Paolo Prinetto,
Monica Lobetti Bodoni:
A Family of Self-Repair SRAM Cores.
IOLTW 2000: 214-218 |
| 72 | EE | Alfredo Benso,
Silvia Chiusano,
Paolo Prinetto:
A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT.
IOLTW 2000: 9-16 |
| 71 | | Alfredo Benso,
Silvia Chiusano,
Paolo Prinetto:
A software development kit for dependable applications in embedded systems.
ITC 2000: 170-178 |
| 70 | | Alfredo Benso,
Stefano Di Carlo,
Giorgio Di Natale,
Paolo Prinetto,
Monica Lobetti Bodoni:
A programmable BIST architecture for clusters of multiple-port SRAMs.
ITC 2000: 557-566 |
| 69 | | Silvia Chiusano,
Paolo Prinetto,
Hans-Joachim Wunderlich:
Non-intrusive BIST for systems-on-a-chip.
ITC 2000: 644-651 |
| 68 | | Alfredo Benso,
Silvia Chiusano,
Stefano Di Carlo,
Paolo Prinetto,
Fabio Ricciato,
Maurizio Spadari,
Yervant Zorian:
HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs.
ITC 2000: 892-901 |
| 67 | EE | Alfredo Benso,
Silvia Cataldo,
Silvia Chiusano,
Paolo Prinetto,
Yervant Zorian:
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures.
J. Electronic Testing 16(3): 179-184 (2000) |
| 1999 |
|---|
| 66 | | Alfredo Benso,
Silvia Cataldo,
Silvia Chiusano,
Paolo Prinetto,
Yervant Zorian:
HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs.
ITC 1999: 1038-1044 |
| 65 | | Alfredo Benso,
Silvia Chiusano,
Paolo Prinetto,
Simone Giovannetti,
Riccardo Mariani,
Silvano Motto:
Testing an MCM for high-energy physics experiments: a case study.
ITC 1999: 38-46 |
| 64 | | Monica Lobetti Bodoni,
Alessio Pricco,
Alfredo Benso,
Silvia Chiusano,
Paolo Prinetto:
An on-line BISTed SRAM IP core.
ITC 1999: 993-1000 |
| 63 | EE | Silvia Chiusano,
Fulvio Corno,
Paolo Prinetto:
RT-level TPG Exploiting High-Level Synthesis Information.
VTS 1999: 341-353 |
| 62 | EE | Fulvio Corno,
Uwe Gläser,
Paolo Prinetto,
Matteo Sonza Reorda,
Heinrich Theodor Vierhaus,
Massimo Violante:
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 191-202 (1999) |
| 61 | EE | Silvia Chiusano,
Fulvio Corno,
Paolo Prinetto:
Exploiting Behavioral Information in Gate-Level ATPG.
J. Electronic Testing 14(1-2): 141-148 (1999) |
| 1998 |
|---|
| 60 | EE | Silvia Chiusano,
Fulvio Corno,
Paolo Prinetto:
A Test Pattern Generation Algorithm Exploiting Behavioral Information.
Asian Test Symposium 1998: 480-485 |
| 59 | EE | Elizabeth M. Rudnick,
Roberto Vietti,
Akilah Ellis,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques.
DATE 1998: 570-576 |
| 58 | EE | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection.
DATE 1998: 670- |
| 57 | EE | Alfredo Benso,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A fault injection environment for microprocessor-based boards.
ITC 1998: 768-773 |
| 56 | EE | Fulvio Corno,
Nicola Gaudenzi,
Paolo Prinetto,
Matteo Sonza Reorda:
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits.
VTS 1998: 424-429 |
| 55 | EE | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A Test Pattern Generation Methodology for Low-Power Consumption.
VTS 1998: 453-459 |
| 54 | EE | Alfredo Benso,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
EXFI: a low-cost fault injection system for embedded microprocessor-based boards.
ACM Trans. Design Autom. Electr. Syst. 3(4): 626-634 (1998) |
| 53 | | Gianpiero Cabodi,
Paolo Camurati,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
The General Product Machine: a New Model for Symbolic FSM Traversal.
Formal Methods in System Design 12(3): 267-289 (1998) |
| 52 | EE | Stefano Barbagallo,
Davide Medina,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Integrating Online and Offline Testing of a Switching Memory.
IEEE Design & Test of Computers 15(1): 63-70 (1998) |
| 1997 |
|---|
| 51 | EE | Silvia Chiusano,
Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Guaranteeing Testability in Re-encoding for Low Power.
Asian Test Symposium 1997: 30-35 |
| 50 | EE | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Giovanni Squillero:
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.
Asian Test Symposium 1997: 56-61 |
| 49 | EE | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG.
Asian Test Symposium 1997: 68-73 |
| 48 | | Mario Baldi,
Fulvio Corno,
Maurizio Rebaudengo,
Paolo Prinetto,
Matteo Sonza Reorda,
Giovanni Squillero:
Simulation-based verification of network protocols performance.
CHARME 1997: 236-251 |
| 47 | EE | Alfredo Benso,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Jaan Raik,
Raimund Ubar:
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments.
DFT 1997: 212-217 |
| 46 | EE | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
New static compaction techniques of test sequences for sequential circuits.
ED&TC 1997: 37-43 |
| 45 | EE | Silvia Chiusano,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Hybrid symbolic-explicit techniques for the graph coloring problem.
ED&TC 1997: 422-426 |
| 44 | EE | Alfredo Benso,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Raimund Ubar:
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs.
ED&TC 1997: 560-565 |
| 43 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Giovanni Squillero:
A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits.
ICCD 1997: 381-386 |
| 42 | EE | S. Chuisano,
Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization.
ICTAI 1997: 133- |
| 41 | | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Testability Analysis and ATPG on Behavioral RT-Level VHDL.
ITC 1997: 753-759 |
| 40 | EE | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits.
SAC 1997: 228-232 |
| 39 | EE | J. Abraham,
P. Frankl,
Christian Landrault,
Meryem Marzouki,
Paolo Prinetto,
Chantal Robach,
Pascale Thévenod-Fosse:
Hardware Test: Can We Learn from Software Testing?
VTS 1997: 320-321 |
| 38 | EE | Silvia Chiusano,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Cellular automata for deterministic sequential test pattern generation.
VTS 1997: 60-67 |
| 1996 |
|---|
| 37 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Maurizio Damiani,
Leonardo Impagliazzo,
G. Sartore:
On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications.
EDCC 1996: 190-202 |
| 36 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits.
HPCN Europe 1996: 454-459 |
| 35 | | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits.
ICTAI 1996: 10-16 |
| 34 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach.
ITC 1996: 39-47 |
| 33 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs.
ITC 1996: 558-564 |
| 32 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits.
PPSN 1996: 792-800 |
| 31 | EE | Stefano Barbagallo,
Monica Lobetti Bodoni,
Davide Medina,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Scan insertion criteria for low design impact.
VTS 1996: 26-31 |
| 30 | EE | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Circular Self-Test Path for FSMs.
IEEE Design & Test of Computers 13(4): 50-60 (1996) |
| 29 | EE | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 991-1000 (1996) |
| 1995 |
|---|
| 28 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Enzo Veiluva:
A PVM tool for automatic test generation on parallel and distributed systems.
HPCN Europe 1995: 39-44 |
| 27 | | Stefano Barbagallo,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Testing a Switching Memory in a Telcommunication System.
ITC 1995: 947-956 |
| 26 | EE | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Enzo Veiluva:
A portable ATPG tool for parallel and distributed systems.
VTS 1995: 29-34 |
| 25 | EE | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda,
Uwe Gläser,
Heinrich Theodor Vierhaus:
Improving topological ATPG with symbolic techniques.
VTS 1995: 338-343 |
| 24 | EE | Paolo Camurati,
Paolo Prinetto,
Matteo Sonza Reorda,
Stefano Barbagallo,
Andrea Burri,
Davide Medina:
Industrial BIST of Embedded RAMs.
IEEE Design & Test of Computers 12(3): 86-95 (1995) |
| 1994 |
|---|
| 23 | | Paolo Camurati,
Fulvio Corno,
Paolo Prinetto,
Catherine Bayol,
Bernard Soulas:
System-Level Modeling and Verification: a Comprehensive Design Methodology.
EDAC-ETC-EUROASIC 1994: 636-640 |
| 22 | EE | Paolo Prinetto,
Fulvio Corno,
Matteo Sonza Reorda:
An experimental analysis of the effectiveness of the circular self-test path technique.
EURO-DAC 1994: 246-251 |
| 21 | EE | Catherine Bayol,
Bernard Soulas,
Dominique Borrione,
Fulvio Corno,
Paolo Prinetto:
A process algebra interpretation of a verification oriented overlanguage of VHDL.
EURO-DAC 1994: 506-511 |
| 20 | | Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Enzo Veiluva:
GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits.
ICTAI 1994: 411-417 |
| 19 | | Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms.
ITC 1994: 240-249 |
| 18 | | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Making the Circular Self-Test Path Technique Effective for Real Circuits.
ITC 1994: 949-957 |
| 1993 |
|---|
| 17 | | Paolo Camurati,
Fulvio Corno,
Paolo Prinetto:
A Methodology for System-Level Design for Verifiability.
CHARME 1993: 80-91 |
| 16 | | Paolo Camurati,
Fulvio Corno,
Paolo Prinetto:
Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation.
CHDL 1993: 31-44 |
| 15 | EE | Gianpiero Cabodi,
Paolo Camurati,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
An approach to sequential circuit diagnosis based on formal verification techniques.
J. Electronic Testing 4(1): 11-17 (1993) |
| 1992 |
|---|
| 14 | EE | Gianpiero Cabodi,
Paolo Camurati,
Fulvio Corno,
Silvano Gai,
Paolo Prinetto,
Matteo Sonza Reorda:
A New Model for Improving symbolic Product Machine Traversal.
DAC 1992: 614-619 |
| 13 | | Gianpiero Cabodi,
Paolo Camurati,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Sequential Circuit Diagnosis Based on Formal Verification Techniques.
ITC 1992: 187-196 |
| 1991 |
|---|
| 12 | | Gianpiero Cabodi,
Paolo Camurati,
Paolo Prinetto,
Matteo Sonza Reorda:
TPDL: Extended Temporal Profile Description Language.
Softw., Pract. Exper. 21(4): 355-374 (1991) |
| 1990 |
|---|
| 11 | | Paolo Camurati,
M. Gilli,
Paolo Prinetto,
Matteo Sonza Reorda:
The Use of Model Checking in ATPG for Sequential Circuits.
CAV 1990: 86-95 |
| 10 | EE | Paolo Camurati,
Antonio Lioy,
Paolo Prinetto,
Matteo Sonza Reorda:
Diagnosis oriented test pattern generation.
EURO-DAC 1990: 470-474 |
| 9 | EE | Paolo Camurati,
Paolo Prinetto,
Matteo Sonza Reorda:
Exact probabilistic testability measures for multi-output circuits.
J. Electronic Testing 1(3): 229-234 (1990) |
| 1989 |
|---|
| 8 | | Dominique Borrione,
Paolo Prinetto:
Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis.
IFIP Congress 1989: 233-240 |
| 1988 |
|---|
| 7 | | Paolo Camurati,
Paolo Prinetto:
Formal Verification of Hardware Correctness: Introduction and Survey of Current Research.
IEEE Computer 21(7): 8-19 (1988) |
| 6 | EE | Paolo Camurati,
P. Gianoglio,
R. Gianoglio,
Paolo Prinetto:
ESTA: an expert system for DFT rule verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(11): 1172-1180 (1988) |
| 1986 |
|---|
| 5 | | Gianpiero Cabodi,
Paolo Camurati,
Paolo Prinetto:
Experiences in Prolog-Based DFT Rule Checking.
FJCC 1986: 909-914 |
| 1985 |
|---|
| 4 | | Fabio Somenzi,
Silvano Gai,
Marco Mezzalama,
Paolo Prinetto:
Testing Strategy and Technique for Macro-Based Circuits.
IEEE Trans. Computers 34(1): 85-90 (1985) |
| 1984 |
|---|
| 3 | EE | Fabio Somenzi,
Silvano Gai,
Marco Mezzalama,
Paolo Prinetto:
PART: Programmable Array Testing Based on a Partitioning Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(2): 142-149 (1984) |
| 1983 |
|---|
| 2 | | Marco Mezzalama,
Paolo Prinetto:
A Hierarchical Description Model for Microcode.
IEEE Trans. Computers 32(5): 478-487 (1983) |
| 1982 |
|---|
| 1 | | Marco Mezzalama,
Paolo Prinetto:
A Machine-independent Approach to Microprogram Synthesis.
Softw., Pract. Exper. 12(10): 985-1010 (1982) |
