| 2007 |
|---|
| 14 | EE | Ka Lok Man,
Andrea Fedeli,
Michele Mercaldi,
Menouer Boubekeur,
Michel P. Schellekens:
SC2SCFL: Automated SystemC to SystemCFL Translation.
SAMOS 2007: 34-45 |
| 13 | EE | Nicola Bombieri,
Franco Fummi,
Graziano Pravadelli,
Andrea Fedeli:
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows.
IEEE Design & Test of Computers 24(2): 140-152 (2007) |
| 12 | EE | Andrea Fedeli,
Franco Fummi,
Graziano Pravadelli:
Properties Incompleteness Evaluation by Functional Verification.
IEEE Trans. Computers 56(4): 528-544 (2007) |
| 2005 |
|---|
| 11 | EE | Nicola Bombieri,
Andrea Fedeli,
Franco Fummi:
Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling.
MEMOCODE 2005: 239-240 |
| 10 | EE | Nicola Bombieri,
Andrea Fedeli,
Franco Fummi:
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling.
MTV 2005: 127-132 |
| 2004 |
|---|
| 9 | EE | Michele Borgatti,
Andrea Fedeli,
Umberto Rossi,
Jean-Luc Lambert,
Imed Moussa,
Franco Fummi,
Cristina Marconcini,
Graziano Pravadelli:
A Verification Methodology for Reconfigurable Systems.
MTV 2004: 85-90 |
| 8 | EE | Giacomo Bucci,
Andrea Fedeli,
Luigi Sassoli,
Enrico Vicario:
Timed State Space Analysis of Real-Time Preemptive Systems.
IEEE Trans. Software Eng. 30(2): 97-111 (2004) |
| 2003 |
|---|
| 7 | EE | Giacomo Bucci,
Andrea Fedeli,
Luigi Sassoli,
Enrico Vicario:
Modeling Flexible Real Time Systems with Preemptive Time Petri Nets.
ECRTS 2003: 279-286 |
| 6 | EE | Giacomo Bucci,
Andrea Fedeli,
Enrico Vicario:
Predicting Timeliness of Reactive Systems under Flexible Scheduling.
ISADS 2003: 125-130 |
| 5 | EE | Franco Fummi,
Graziano Pravadelli,
Andrea Fedeli,
Umberto Rossi,
Franco Toto:
On the Use of a High-Level Fault Model to Check Properties Incompleteness.
MEMOCODE 2003: 145-152 |
| 4 | EE | Giacomo Bucci,
Andrea Fedeli,
Enrico Vicario:
Specification and Simulation of Real Time Concurrent Systems Using Standard SDL Tools.
SDL Forum 2003: 203-217 |
| 2002 |
|---|
| 3 | EE | Paolo Azzoni,
Andrea Fedeli,
Franco Fummi,
Graziano Pravadelli,
Umberto Rossi,
Franco Toto:
An error simulation based approach to measure error coverage of formal properties.
ACM Great Lakes Symposium on VLSI 2002: 53-58 |
| 2 | EE | Joel Blasquez,
Marten van Hulst,
Andrea Fedeli,
Jean-Luc Lambert,
Dominique Borrione,
Coby Hanoch,
Pierre Bricaud:
Formal Verification Techniques: Industrial Status and Perspectives.
DATE 2002: 1050-1051 |
| 2001 |
|---|
| 1 | EE | Umberto Rossi,
Andrea Fedeli,
Marco Boschini,
Franco Toto:
Concrete Impact of Formal Verification on Quality in IP Design and Implementation.
ISQED 2001: 38-43 |
