| 2009 |
|---|
| 74 | EE | Sudeep Pasricha,
Nikil Dutt,
Fadi J. Kurdahi:
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.
VLSI Design 2009: 499-504 |
| 73 | EE | Sudeep Pasricha,
Young-Hwan Park,
Nikil D. Dutt,
Fadi J. Kurdahi:
System-level PVT variation-aware power exploration of on-chip communication architectures.
ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
| 2008 |
|---|
| 72 | EE | Young-Hwan Park,
Sudeep Pasricha,
Fadi J. Kurdahi,
Nikil Dutt:
Methodology for multi-granularity embedded processor power model generation for an ESL design flow.
CODES+ISSS 2008: 255-260 |
| 71 | EE | Amin Khajeh Djahromi,
Minyoung Kim,
Nikil Dutt,
Ahmed M. Eltawil,
Fadi J. Kurdahi:
Cross-layer co-exploration of exploiting error resilience for video over wireless applications.
ESTImedia 2008: 13-18 |
| 70 | EE | Aseem Gupta,
Nikil D. Dutt,
Fadi J. Kurdahi,
Kamal S. Khouri,
Magdy S. Abadir:
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.
ISQED 2008: 470-475 |
| 69 | EE | Fadi J. Kurdahi,
Nikil Dutt,
Ahmed M. Eltawil,
Sani R. Nassif:
Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.
VLSI Design 2008: 14-15 |
| 68 | EE | Sudeep Pasricha,
Young-Hwan Park,
Fadi J. Kurdahi,
Nikil Dutt:
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.
VLSI Design 2008: 363-370 |
| 67 | EE | Deepa Kannan,
Aseem Gupta,
Aviral Shrivastava,
Nikil D. Dutt,
Fadi J. Kurdahi:
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.
VLSI Design 2008: 421-427 |
| 2007 |
|---|
| 66 | EE | Aseem Gupta,
Nikil D. Dutt,
Fadi J. Kurdahi,
Kamal S. Khouri,
Magdy S. Abadir:
LEAF: A System Level Leakage-Aware Floorplanner for SoCs.
ASP-DAC 2007: 274-279 |
| 65 | EE | Kang Yi,
Shih-Yang Cheng,
Young-Hwan Park,
Fadi J. Kurdahi,
Ahmed M. Eltawil:
An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories.
Asia-Pacific Computer Systems Architecture Conference 2007: 102-113 |
| 64 | EE | Fadi J. Kurdahi,
Ahmed M. Eltawil,
Amin Khajeh Djahromi,
Mohammad A. Makhzan,
Stanley Cheng:
Error-Aware Design.
DSD 2007: 8-15 |
| 63 | EE | Amin Khajeh,
Shih-Yang Cheng,
Ahmed M. Eltawil,
Fadi J. Kurdahi:
Power Management for Cognitive Radio Platforms.
GLOBECOM 2007: 4066-4070 |
| 62 | EE | Mohammad A. Makhzan,
Amin Khajeh Djahromi,
Ahmed M. Eltawil,
Fadi J. Kurdahi:
Limits on voltage scaling for caches utilizing fault tolerant techniques.
ICCD 2007: 488-495 |
| 61 | EE | Young-Hwan Park,
Sudeep Pasricha,
Fadi J. Kurdahi,
Nikil Dutt:
System level power estimation methodology with H.264 decoder prediction IP case study.
ICCD 2007: 601-608 |
| 60 | EE | Amin Khajeh Djahromi,
Ahmed M. Eltawil,
Fadi J. Kurdahi,
Rouwaida Kanj:
Cross Layer Error Exploitation for Aggressive Voltage Scaling.
ISQED 2007: 192-197 |
| 59 | EE | Aseem Gupta,
Nikil D. Dutt,
Fadi J. Kurdahi,
Kamal S. Khouri,
Magdy S. Abadir:
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.
VLSI Design 2007: 559-564 |
| 58 | EE | Amin Khajeh Djahromi,
Ahmed M. Eltawil,
Fadi J. Kurdahi:
Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design.
VTC Spring 2007: 2600-2604 |
| 57 | EE | Chunhui Zhang,
Fadi J. Kurdahi:
Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications.
International Journal of Parallel Programming 35(1): 63-98 (2007) |
| 56 | EE | Chunhui Zhang,
Yun Long,
Fadi J. Kurdahi:
A scalable embedded JPEG 2000 architecture.
Journal of Systems Architecture 53(8): 524-538 (2007) |
| 2006 |
|---|
| 55 | EE | Kang Yi,
Kyeong-Hoon Jung,
Shih-Yang Cheng,
Young-Hwan Park,
Fadi J. Kurdahi,
Ahmed M. Eltawil:
Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs.
Asia-Pacific Computer Systems Architecture Conference 2006: 295-308 |
| 54 | EE | Aseem Gupta,
Nikil D. Dutt,
Fadi J. Kurdahi,
Kamal S. Khouri,
Magdy S. Abadir:
Floorplan driven leakage power aware IP-based SoC design space exploration.
CODES+ISSS 2006: 118-123 |
| 53 | EE | Sudeep Pasricha,
Young-Hwan Park,
Fadi J. Kurdahi,
Nikil D. Dutt:
System-level power-performance trade-offs in bus matrix communication architecture synthesis.
CODES+ISSS 2006: 300-305 |
| 52 | EE | Fadi J. Kurdahi,
Ahmed M. Eltawil,
Young-Hwan Park,
Rouwaida Kanj,
Sani R. Nassif:
System-Level SRAM Yield Enhancement.
ISQED 2006: 179-184 |
| 51 | EE | Dhananjay Kulkarni,
Walid A. Najjar,
Robert Rinker,
Fadi J. Kurdahi:
Compile-time area estimation for LUT-based FPGAs.
ACM Trans. Design Autom. Electr. Syst. 11(1): 104-122 (2006) |
| 2005 |
|---|
| 50 | EE | Chunhui Zhang,
Fadi J. Kurdahi:
On combining iteration space tiling with data space tiling for scratch-pad memory systems.
ASP-DAC 2005: 973-976 |
| 49 | EE | Chunhui Zhang,
Yun Long,
Fadi J. Kurdahi:
A Scalable Embedded JPEG2000 Architecture.
SAMOS 2005: 334-343 |
| 2003 |
|---|
| 48 | EE | Behzad Mohebbi,
Eliseu Chavez Filho,
Rafael Maestre,
Mark Davies,
Fadi J. Kurdahi:
A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core.
CODES+ISSS 2003: 103-108 |
| 47 | EE | Girish Venkataramani,
Walid A. Najjar,
Fadi J. Kurdahi,
Nader Bagherzadeh,
A. P. Wim Böhm,
Jeffrey Hammes:
Automatic compilation to a coarse-grained reconfigurable system-opn-chip.
ACM Trans. Embedded Comput. Syst. 2(4): 560-589 (2003) |
| 2002 |
|---|
| 46 | EE | Marcos Sanchez-Elez,
Milagros Fernández,
Rafael Maestre,
Rafael Maestre,
Fadi J. Kurdahi,
Román Hermida,
Nader Bagherzadeh:
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures.
DATE 2002: 547-552 |
| 45 | EE | Hooman Parizi,
Afshin Niktash,
Nader Bagherzadeh,
Fadi J. Kurdahi:
MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note).
Euro-Par 2002: 844-848 |
| 44 | EE | Dhananjay Kulkarni,
Walid A. Najjar,
Robert Rinker,
Fadi J. Kurdahi:
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems.
FCCM 2002: 239- |
| 43 | EE | Fadi J. Kurdahi:
Guest editorial special issue on system synthesis.
IEEE Trans. VLSI Syst. 10(4): 377-378 (2002) |
| 2001 |
|---|
| 42 | EE | Girish Venkataramani,
Walid A. Najjar,
Fadi J. Kurdahi,
Nader Bagherzadeh,
A. P. Wim Böhm:
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture.
CASES 2001: 116-125 |
| 41 | EE | Jinfeng Liu,
Pai H. Chou,
Nader Bagherzadeh,
Fadi J. Kurdahi:
A constraint-based application model and scheduling techniques for power-aware systems.
CODES 2001: 153-158 |
| 40 | EE | Jinfeng Liu,
Pai H. Chou,
Nader Bagherzadeh,
Fadi J. Kurdahi:
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems.
DAC 2001: 840-845 |
| 39 | | Marcos Sanchez-Elez,
Milagros Fernández,
Román Hermida,
Rafael Maestre,
Fadi J. Kurdahi,
Nader Bagherzadeh:
A data scheduler for multi-context reconfigurable architectures.
ISSS 2001: 177-182 |
| 38 | EE | Rafael Maestre,
Fadi J. Kurdahi,
Milagros Fernández,
Román Hermida,
Nader Bagherzadeh,
Hartej Singh:
A framework for reconfigurable computing: task scheduling and context management.
IEEE Trans. VLSI Syst. 9(6): 858-873 (2001) |
| 2000 |
|---|
| 37 | EE | Hartej Singh,
Guangming Lu,
Eliseu M. Chaves Filho,
Rafael Maestre,
Ming-Hau Lee,
Fadi J. Kurdahi,
Nader Bagherzadeh:
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications.
DAC 2000: 573-578 |
| 36 | EE | Rafael Maestre,
Milagros Fernández,
Román Hermida,
Fadi J. Kurdahi,
Nader Bagherzadeh,
Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
FCCM 2000: 297-298 |
| 35 | EE | Rafael Maestre,
Milagros Fernández,
Román Hermida,
Fadi J. Kurdahi,
Nader Bagherzadeh,
Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
ICCD 2000: 575-576 |
| 34 | EE | Rafael Maestre,
Fadi J. Kurdahi,
Milagros Fernández,
Nader Bagherzadeh,
Hartej Singh:
Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization.
ISSS 2000: 107-114 |
| 33 | | Fadi J. Kurdahi,
Nader Bagherzadeh,
Peter Athanas,
Jose L. Muñoz:
Guest Editors' Introduction: Configurable Computing.
IEEE Design & Test of Computers 17(1): 17-19 (2000) |
| 32 | EE | Hartej Singh,
Ming-Hau Lee,
Guangming Lu,
Fadi J. Kurdahi,
Nader Bagherzadeh,
Eliseu M. Chaves Filho:
MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications.
IEEE Trans. Computers 49(5): 465-481 (2000) |
| 31 | EE | Ming-Hau Lee,
Hartej Singh,
Guangming Lu,
Nader Bagherzadeh,
Fadi J. Kurdahi,
Eliseu M. Chaves Filho,
Vladimir Castro Alves:
Design and Implementation of the MorphoSys Reconfigurable Computing Processor.
VLSI Signal Processing 24(2-3): 147-164 (2000) |
| 1999 |
|---|
| 30 | EE | Rafael Maestre,
Fadi J. Kurdahi,
Nader Bagherzadeh,
Hartej Singh,
Román Hermida,
Milagros Fernández:
Kernel Scheduling in Reconfigurable Computing.
DATE 1999: 90-96 |
| 29 | EE | Guangming Lu,
Hartej Singh,
Ming-Hau Lee,
Nader Bagherzadeh,
Fadi J. Kurdahi,
Eliseu M. Chaves Filho:
The MorphoSys Parallel Reconfigurable System.
Euro-Par 1999: 727-734 |
| 28 | EE | Guangming Lu,
Hartej Singh,
Ming-Hau Lee,
Nader Bagherzadeh,
Fadi J. Kurdahi,
Eliseu M. Chaves Filho,
Vladimir Castro Alves:
The MorphoSys Dynamically Reconfigurable System-on-Chip.
Evolvable Hardware 1999: 152-160 |
| 27 | | Guangming Lu,
Ming-Hau Lee,
Hartej Singh,
Nader Bagherzadeh,
Fadi J. Kurdahi,
Eliseu M. Chaves Filho:
MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application.
IPPS/SPDP Workshops 1999: 661-669 |
| 26 | EE | Douglas M. Blough,
Fadi J. Kurdahi,
Seong Yong Ohm:
High-level synthesis of recoverable VLSI microarchitectures.
IEEE Trans. VLSI Syst. 7(4): 401-410 (1999) |
| 25 | EE | Min Xu,
Fadi J. Kurdahi:
Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs.
IEEE Trans. VLSI Syst. 7(4): 411-418 (1999) |
| 1998 |
|---|
| 24 | EE | Min Xu,
Fadi J. Kurdahi:
Layout-Driven High Level Synthesis for FPGA Based Architectures.
DATE 1998: 446-450 |
| 23 | EE | Dirk Stroobandt,
Fadi J. Kurdahi:
On the Characterization of Multi-Point Nets in Electronic Designs.
Great Lakes Symposium on VLSI 1998: 344- |
| 1997 |
|---|
| 22 | EE | Min Xu,
Fadi J. Kurdahi:
RTL synthesis with physical and controller information.
ED&TC 1997: 299-303 |
| 21 | EE | Min Xu,
Fadi J. Kurdahi:
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators.
ACM Trans. Design Autom. Electr. Syst. 2(4): 312-343 (1997) |
| 20 | EE | Seong Yong Ohm,
Fadi J. Kurdahi,
Nikil D. Dutt:
A unified lower bound estimation technique for high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 458-472 (1997) |
| 19 | EE | Douglas M. Blough,
Fadi J. Kurdahi,
Seong Yong Ohm:
Optimal algorithms for recovery point insertion in recoverable microarchitectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 945-955 (1997) |
| 1996 |
|---|
| 18 | EE | Min Xu,
Fadi J. Kurdahi:
Layout-Driven RTL Binding Techniques for High-Level Synthesis.
ISSS 1996: 33-38 |
| 17 | EE | A. Sriram,
Fadi J. Kurdahi:
Behavioral Modeling of an ATM Switch using SpecCharts.
VLSI Design 1996: 19-22 |
| 1995 |
|---|
| 16 | | Douglas M. Blough,
Fadi J. Kurdahi,
Seong Yong Ohm:
Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures.
FTCS 1995: 50-59 |
| 15 | EE | Seong Yong Ohm,
Fadi J. Kurdahi,
Nikil Dutt,
Min Xu:
A comprehensive estimation technique for high-level synthesis.
ISSS 1995: 122-127 |
| 1994 |
|---|
| 14 | | Champaka Ramachandran,
Fadi J. Kurdahi:
Incorporating the Controller Effects During Register Transfer Level Synthesis.
EDAC-ETC-EUROASIC 1994: 308-313 |
| 13 | EE | Seong Yong Ohm,
Fadi J. Kurdahi,
Nikil D. Dutt:
Comprehensive lower bound estimation from behavioral descriptions.
ICCAD 1994: 182-187 |
| 12 | | Pradip K. Jha,
Champaka Ramachandran,
Nikil D. Dutt,
Fadi J. Kurdahi:
An Empirical Study on the Effects of Physical Design in High-Level Synthesis.
VLSI Design 1994: 11-16 |
| 11 | EE | Lars W. Hagen,
Andrew B. Kahng,
Fadi J. Kurdahi,
Champaka Ramachandran:
On the intrinsic Rent parameter and spectra-based partitioning methodologies.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 27-37 (1994) |
| 10 | EE | Champaka Ramachandran,
Fadi J. Kurdahi:
Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1450-1460 (1994) |
| 1993 |
|---|
| 9 | EE | Fadi J. Kurdahi,
Champaka Ramachandran:
Evaluating layout area tradeoffs for high level applications.
IEEE Trans. VLSI Syst. 1(1): 46-55 (1993) |
| 8 | EE | D. Sreenivasa Rao,
Fadi J. Kurdahi:
Hierarchical design space exploration for a class of digital systems.
IEEE Trans. VLSI Syst. 1(3): 282-295 (1993) |
| 7 | EE | D. Sreenivasa Rao,
Fadi J. Kurdahi:
On clustering for maximal regularity extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1198-1208 (1993) |
| 1992 |
|---|
| 6 | EE | D. Sreenivasa Rao,
Fadi J. Kurdahi:
Partitioning by Regularity Extraction.
DAC 1992: 235-238 |
| 5 | EE | Champaka Ramachandran,
Fadi J. Kurdahi,
Daniel Gajski,
Allen C.-H. Wu,
Viraphol Chaiyakul:
Accurate layout area and delay modeling for system level design.
ICCAD 1992: 355-361 |
| 1991 |
|---|
| 4 | | James J. Kim,
Fadi J. Kurdahi,
Nohbyung Park:
Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths.
ICCAD 1991: 30-33 |
| 1989 |
|---|
| 3 | EE | Fadi J. Kurdahi,
Alice C. Parker:
Techniques for area estimation of VLSI layouts.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(1): 81-92 (1989) |
| 1987 |
|---|
| 2 | EE | Fadi J. Kurdahi,
Alice C. Parker:
REAL: a program for REgister ALlocation.
DAC 1987: 210-215 |
| 1986 |
|---|
| 1 | EE | Fadi J. Kurdahi,
Alice C. Parker:
PLEST: a program for area estimation of VLSI integrated circuits.
DAC 1986: 467-473 |
