2008 |
31 | EE | Raimund Ubar,
Sergei Devadze,
Jaan Raik,
Artur Jutman:
Parallel fault backtracing for calculation of fault coverage.
ASP-DAC 2008: 667-672 |
30 | EE | Jaan Raik,
Uljana Reinsalu,
Raimund Ubar,
Maksim Jenihhin,
Peeter Ellervee:
Code Coverage Analysis using High-Level Decision Diagrams.
DDECS 2008: 201-206 |
29 | EE | Eero Ivask,
Jaan Raik,
Raimund Ubar:
Web-Based Framework for Parallel Distributed Test.
DDECS 2008: 271-274 |
28 | EE | Raimund Ubar,
Sergei Devadze,
Maksim Jenihhin,
Jaan Raik,
Gert Jervan,
Peeter Ellervee:
Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance.
DELTA 2008: 222-227 |
27 | EE | Eero Ivask,
Jaan Raik,
Raimund Ubar:
Distributed Approach for Genetic Test Generation in the Field of Digital Electronics.
IDC 2008: 127-136 |
26 | EE | Jaan Raik,
Raimund Ubar,
Taavi Viilukas,
Maksim Jenihhin:
Mixed hierarchical-functional fault models for targeting sequential cores.
Journal of Systems Architecture - Embedded Systems Design 54(3-4): 465-477 (2008) |
25 | EE | Raimund Ubar,
Sergei Kostin,
Jaan Raik:
Embedded fault diagnosis in digital systems with BIST.
Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 279-287 (2008) |
2007 |
24 | | Maksim Jenihhin,
Jaan Raik,
Raimund Ubar,
Witold A. Pleskacz,
Michal Rakowski:
Layout to Logic Defect Analysis for Hierarchical Test Generation.
DDECS 2007: 35-40 |
23 | EE | Raimund Ubar,
Sergei Kostin,
Jaan Raik,
Teet Evartson,
Harri Lensen:
Fault Diagnosis in Integrated Circuits with BIST.
DSD 2007: 604-610 |
22 | EE | Jaan Raik,
Raimund Ubar,
Anna Krivenko,
Margus Kruus:
Hierarchical Identification of Untestable Faults in Sequential Circuits.
DSD 2007: 668-671 |
21 | EE | Raimund Ubar,
Sergei Devadze,
Jaan Raik,
Artur Jutman:
Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.
European Test Symposium 2007: 131-136 |
20 | EE | Jaan Raik,
Raimund Ubar,
Vineeth Govind:
Test Configurations for Diagnosing Faulty Links in NoC Switches.
European Test Symposium 2007: 29-34 |
2006 |
19 | EE | Jaan Raik,
Raimund Ubar,
Taavi Viilukas:
High-Level Decision Diagram based Fault Models for Targeting FSMs.
DSD 2006: 353-358 |
2005 |
18 | EE | Artur Jutman,
Jaan Raik,
Raimund Ubar,
V. Vislogubov:
An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform.
DSD 2005: 412-419 |
17 | EE | Jaan Raik,
Peeter Ellervee,
Valentin Tihhomirov,
Raimund Ubar:
Improved Fault Emulation for Synchronous Sequential Circuits.
DSD 2005: 72-78 |
16 | EE | Joachim Sudbrock,
Jaan Raik,
Raimund Ubar,
Wieslaw Kuzmicz,
Witold A. Pleskacz:
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.
DSD 2005: 79-82 |
15 | EE | Jaan Raik,
Raimund Ubar,
Sergei Devadze,
Artur Jutman:
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs.
EDCC 2005: 332-344 |
14 | EE | Jaan Raik,
Tanel Nõmmeots,
Raimund Ubar:
A New Testability Calculation Method to Guide RTL Test Generation.
J. Electronic Testing 21(1): 71-82 (2005) |
2004 |
13 | EE | Peeter Ellervee,
Jaan Raik,
Valentin Tihhomirov,
Kalle Tammemäe:
Evaluating Fault Emulation on FPGA.
FPL 2004: 354-363 |
12 | | Eero Ivask,
Jaan Raik,
Raimund Ubar,
André Schneider:
Web-Based Environment for Digital Electronics Test Tools.
Virtual Enterprises and Collaborative Networks 2004: 435-442 |
2002 |
11 | EE | André Schneider,
Karl-Heinz Diener,
Eero Ivask,
Jaan Raik,
Raimund Ubar,
P. Miklos,
T. Cibáková,
Elena Gramatová:
Internet-Based Collaborative Test Generation with MOSCITO.
DATE 2002: 221-226 |
10 | EE | Raimund Ubar,
Jaan Raik,
Eero Ivask,
Marina Brik:
Multi-Level Fault Simulation of Digital Systems on Decision Diagrams.
DELTA 2002: 86-91 |
9 | EE | T. Cibáková,
María Fischerová,
Elena Gramatová,
Wieslaw Kuzmicz,
Witold A. Pleskacz,
Jaan Raik,
Raimund Ubar:
Hierarchical test generation for combinational circuits with real defects coverage.
Microelectronics Reliability 42(7): 1141-1149 (2002) |
2001 |
8 | EE | Wieslaw Kuzmicz,
Witold A. Pleskacz,
Jaan Raik,
Raimund Ubar:
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits.
ISQED 2001: 365-371 |
7 | EE | Mykola Blyzniuk,
Irena Kazymyra,
Wieslaw Kuzmicz,
Witold A. Pleskacz,
Jaan Raik,
Raimund Ubar:
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement.
Microelectronics Reliability 41(12): 2023-2040 (2001) |
2000 |
6 | EE | Adam Morawiec,
Raimund Ubar,
Jaan Raik:
Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams.
DATE 2000: 743 |
5 | EE | Raimund Ubar,
Jaan Raik:
Efficient Hierarchical Approach to Test Generation for Digital Systems.
ISQED 2000: 189-196 |
4 | EE | Jaan Raik,
Raimund Ubar:
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations.
J. Electronic Testing 16(3): 213-226 (2000) |
1999 |
3 | EE | Raimund Ubar,
Jaan Raik,
Adam Morawiec:
Cycle-based Simulation with Decision Diagrams.
DATE 1999: 454-458 |
2 | EE | Jaan Raik,
Raimund Ubar:
Sequential Circuit Test Generation Using Decision Diagram Models.
DATE 1999: 736-740 |
1997 |
1 | EE | Alfredo Benso,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Jaan Raik,
Raimund Ubar:
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments.
DFT 1997: 212-217 |