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Jaan Raik

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2008
31EERaimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Parallel fault backtracing for calculation of fault coverage. ASP-DAC 2008: 667-672
30EEJaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee: Code Coverage Analysis using High-Level Decision Diagrams. DDECS 2008: 201-206
29EEEero Ivask, Jaan Raik, Raimund Ubar: Web-Based Framework for Parallel Distributed Test. DDECS 2008: 271-274
28EERaimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee: Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227
27EEEero Ivask, Jaan Raik, Raimund Ubar: Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. IDC 2008: 127-136
26EEJaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin: Mixed hierarchical-functional fault models for targeting sequential cores. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 465-477 (2008)
25EERaimund Ubar, Sergei Kostin, Jaan Raik: Embedded fault diagnosis in digital systems with BIST. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 279-287 (2008)
2007
24 Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski: Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40
23EERaimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen: Fault Diagnosis in Integrated Circuits with BIST. DSD 2007: 604-610
22EEJaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus: Hierarchical Identification of Untestable Faults in Sequential Circuits. DSD 2007: 668-671
21EERaimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. European Test Symposium 2007: 131-136
20EEJaan Raik, Raimund Ubar, Vineeth Govind: Test Configurations for Diagnosing Faulty Links in NoC Switches. European Test Symposium 2007: 29-34
2006
19EEJaan Raik, Raimund Ubar, Taavi Viilukas: High-Level Decision Diagram based Fault Models for Targeting FSMs. DSD 2006: 353-358
2005
18EEArtur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov: An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. DSD 2005: 412-419
17EEJaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar: Improved Fault Emulation for Synchronous Sequential Circuits. DSD 2005: 72-78
16EEJoachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz: Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD 2005: 79-82
15EEJaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman: Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC 2005: 332-344
14EEJaan Raik, Tanel Nõmmeots, Raimund Ubar: A New Testability Calculation Method to Guide RTL Test Generation. J. Electronic Testing 21(1): 71-82 (2005)
2004
13EEPeeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe: Evaluating Fault Emulation on FPGA. FPL 2004: 354-363
12 Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider: Web-Based Environment for Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks 2004: 435-442
2002
11EEAndré Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová: Internet-Based Collaborative Test Generation with MOSCITO. DATE 2002: 221-226
10EERaimund Ubar, Jaan Raik, Eero Ivask, Marina Brik: Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. DELTA 2002: 86-91
9EET. Cibáková, María Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Hierarchical test generation for combinational circuits with real defects coverage. Microelectronics Reliability 42(7): 1141-1149 (2002)
2001
8EEWieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED 2001: 365-371
7EEMykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectronics Reliability 41(12): 2023-2040 (2001)
2000
6EEAdam Morawiec, Raimund Ubar, Jaan Raik: Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. DATE 2000: 743
5EERaimund Ubar, Jaan Raik: Efficient Hierarchical Approach to Test Generation for Digital Systems. ISQED 2000: 189-196
4EEJaan Raik, Raimund Ubar: Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. Electronic Testing 16(3): 213-226 (2000)
1999
3EERaimund Ubar, Jaan Raik, Adam Morawiec: Cycle-based Simulation with Decision Diagrams. DATE 1999: 454-458
2EEJaan Raik, Raimund Ubar: Sequential Circuit Test Generation Using Decision Diagram Models. DATE 1999: 736-740
1997
1EEAlfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar: Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217

Coauthor Index

1Alfredo Benso [1]
2Mykola Blyzniuk [7]
3Marina Brik [10]
4T. Cibáková [9] [11]
5Sergei Devadze [15] [21] [28] [31]
6Karl-Heinz Diener [11]
7Peeter Ellervee [13] [17] [28] [30]
8Teet Evartson [23]
9María Fischerová [9]
10Vineeth Govind [20]
11Elena Gramatová [9] [11]
12Eero Ivask [10] [11] [12] [27] [29]
13Maksim Jenihhin [24] [26] [28] [30]
14Gert Jervan [28]
15Artur Jutman [15] [18] [21] [31]
16Irena Kazymyra [7]
17Sergei Kostin [23] [25]
18Anna Krivenko [22]
19Margus Kruus [22]
20Wieslaw Kuzmicz [7] [8] [9] [16]
21Harri Lensen [23]
22P. Miklos [11]
23Adam Morawiec [3] [6]
24Tanel Nõmmeots [14]
25Witold A. Pleskacz [7] [8] [9] [16] [24]
26Paolo Prinetto [1]
27Michal Rakowski [24]
28Maurizio Rebaudengo [1]
29Uljana Reinsalu [30]
30Matteo Sonza Reorda [1]
31André Schneider [11] [12]
32Joachim Sudbrock [16]
33Kalle Tammemäe [13]
34Valentin Tihhomirov [13] [17]
35Raimund Ubar [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31]
36Taavi Viilukas [19] [26]
37V. Vislogubov [18]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)