| 2008 |
|---|
| 27 | EE | Manitra Rakotoarisoa,
Enric Pastor:
BMC Encoding for Concurrent Systems.
SCCC 2008: 127-134 |
| 2007 |
|---|
| 26 | EE | Juan López,
Pablo Royo,
Enric Pastor,
Cristina Barrado,
Eduard Santamaria:
A middleware architecture for unmanned aircraft avionics.
Middleware (Demos and Posters) 2007: 24 |
| 2005 |
|---|
| 25 | EE | Enric Pastor,
Marco A. Peña,
Marc Solé:
TRANSYT: A Tool for the Verification of Asynchronous Concurrent Systems.
CAV 2005: 424-428 |
| 2004 |
|---|
| 24 | EE | Marc Solé,
Enric Pastor:
Evaluating Symbolic Traversal Algorithms Applied to Asynchronous Concurrent Systems.
ACSD 2004: 207-216 |
| 2003 |
|---|
| 23 | EE | Enric Pastor,
Marco A. Peña:
Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems.
CHARME 2003: 378-393 |
| 22 | EE | Enric Pastor,
Marco A. Peña:
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems.
DATE 2003: 11158-11159 |
| 2002 |
|---|
| 21 | EE | Josep Carmona,
Jordi Cortadella,
Enric Pastor:
Synthesis of Reactive Systems: Application to Asynchronous Circuit Design.
Concurrency and Hardware Design 2002: 108-151 |
| 20 | EE | Marco A. Peña,
Jordi Cortadella,
Alexander B. Smirnov,
Enric Pastor:
A Case Study for the Verification of Complex Timed Circuits: IPCMOS.
DATE 2002: 44-53 |
| 19 | EE | Marc Solé,
Enric Pastor:
Traversal Techniques for Concurrent Systems.
FMCAD 2002: 220-237 |
| 18 | | Josep Carmona,
Jordi Cortadella,
Enric Pastor:
A structural encoding technique for the synthesis of asynchronous circuits.
Fundam. Inform. 50(2): 135-154 (2002) |
| 2001 |
|---|
| 17 | EE | Josep Carmona,
Jordi Cortadella,
Enric Pastor:
A structural encoding technique for the synthesis of asynchronous circuits.
ACSD 2001: 157-166 |
| 16 | EE | Enric Pastor,
Jordi Cortadella,
Oriol Roig:
Symbolic Analysis of Bounded Petri Nets.
IEEE Trans. Computers 50(5): 432-448 (2001) |
| 2000 |
|---|
| 15 | EE | Marco A. Peña,
Jordi Cortadella,
Enric Pastor,
Alex Kondratyev:
Formal Verification of Safety Properties in Timed Circuits.
ASYNC 2000: 2-11 |
| 1999 |
|---|
| 14 | EE | Enric Pastor,
Jordi Cortadella,
Marco A. Peña:
Structural Methods to Improve the Symbolic Analysis of Petri Nets.
ICATPN 1999: 26-45 |
| 13 | EE | Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Enric Pastor,
Alexandre Yakovlev:
Decomposition and technology mapping of speed-independent circuits using Boolean relations.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1221-1236 (1999) |
| 1998 |
|---|
| 12 | EE | Enric Pastor,
Jordi Cortadella:
Efficient Encoding Schemes for Symbolic Analysis of Petri Nets.
DATE 1998: 790-795 |
| 11 | EE | Enric Pastor,
Jordi Cortadella,
Alex Kondratyev,
Oriol Roig:
Structural methods for the synthesis of speed-independent circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1108-1129 (1998) |
| 1997 |
|---|
| 10 | EE | Alexei L. Semenov,
Alexandre Yakovlev,
Enric Pastor,
Marco A. Peña,
Jordi Cortadella,
Luciano Lavagno:
Partial order based approach to synthesis of speed-independent circuits.
ASYNC 1997: 254- |
| 9 | EE | Alexei L. Semenov,
Alexandre Yakovlev,
Enric Pastor,
Marco A. Peña,
Jordi Cortadella:
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment.
DAC 1997: 16-21 |
| 8 | EE | Oriol Roig,
Jordi Cortadella,
Marco A. Peña,
Enric Pastor:
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits.
DAC 1997: 620-625 |
| 7 | EE | Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Enric Pastor,
Alexandre Yakovlev:
Decomposition and technology mapping of speed-independent circuits using Boolean relations.
ICCAD 1997: 220-227 |
| 1995 |
|---|
| 6 | EE | Oriol Roig,
Jordi Cortadella,
Enric Pastor:
Hierarchical gate-level verification of speed-independent circuits.
ASYNC 1995: 128-137 |
| 5 | | Oriol Roig,
Jordi Cortadella,
Enric Pastor:
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets.
Application and Theory of Petri Nets 1995: 374-391 |
| 4 | EE | Enric Pastor,
Jordi Cortadella,
Oriol Roig:
A new look at the conditions for the synthesis of speed-independent circuits.
Great Lakes Symposium on VLSI 1995: 230- |
| 1994 |
|---|
| 3 | | Enric Pastor,
Oriol Roig,
Jordi Cortadella,
Rosa M. Badia:
Petri Net Analysis Using Boolean Manipulation.
Application and Theory of Petri Nets 1994: 416-435 |
| 1993 |
|---|
| 2 | EE | Enric Pastor,
Jordi Cortadella:
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs.
ICCAD 1993: 250-254 |
| 1 | | Enric Pastor,
Jordi Cortadella:
An Efficient Unique State Coding Algorithm for Signal Transition Graphs.
ICCD 1993: 174-177 |
