| 2004 |
|---|
| 10 | EE | Stephen Pateras:
Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both.
ITC 2004: 1413 |
| 2003 |
|---|
| 9 | EE | Stephen Pateras:
Achieving At-Speed Structural Test.
IEEE Design & Test of Computers 20(5): 26-33 (2003) |
| 2002 |
|---|
| 8 | EE | Stephen Pateras:
Embedded Diagnosis IP.
DATE 2002: 242-243 |
| 7 | EE | Stephen Pateras:
IP for Embedded Diagnosis.
IEEE Design & Test of Computers 19(3): 46-55 (2002) |
| 2000 |
|---|
| 6 | | Martin Bell,
Givargis Danialy,
Michael C. Howells,
Stephen Pateras:
Bridging the gap between embedded test and ATE.
ITC 2000: 55-63 |
| 1999 |
|---|
| 5 | | Benoit Nadeau-Dostie,
Jean-Francois Cote,
Harry Hulvershorn,
Stephen Pateras:
An embedded technique for at-speed interconnect testing.
ITC 1999: 431-438 |
| 1997 |
|---|
| 4 | EE | William V. Huott,
Timothy J. Koprowski,
Bryan J. Robbins,
Mary P. Kusko,
Stephen Pateras,
Dale E. Hoffman,
Timothy G. McNamara,
Thomas J. Snethen:
Advanced microprocessor test strategy and methodology.
IBM Journal of Research and Development 41(4&5): 611-628 (1997) |
| 1995 |
|---|
| 3 | | Stephen Pateras,
Martin S. Schmookler:
Avoiding Unknown States When Scanning Mutually Exclusive Latches.
ITC 1995: 311-318 |
| 1991 |
|---|
| 2 | EE | Stephen Pateras,
Janusz Rajski:
Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits.
DAC 1991: 347-352 |
| 1 | | Stephen Pateras,
Janusz Rajski:
Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits.
ITC 1991: 473-482 |
