Patrick Groeneveld

2006
17	EE	Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen: Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip. VLSI-SoC 2006: 80-85
2005
16		Patrick Groeneveld, Louis Scheffer: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005 ACM 2005
15	EE	Jurjen Westra, Patrick Groeneveld: Post-Placement Pin Optimiztion. ISVLSI 2005: 238-243
14	EE	Jurjen Westra, Patrick Groeneveld: Towards Integration of Quadratic Placement and Pin Assignment. ISVLSI 2005: 284-286
13	EE	Jurjen Westra, Patrick Groeneveld: Is probabilistic congestion estimation worthwhile? SLIP 2005: 99-106
2004
12		Charles J. Alpert, Patrick Groeneveld: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004 ACM 2004
11	EE	Francky Catthoor, Andrea Cuomo, Grant Martin, Patrick Groeneveld, Rudy Lauwereins, Karen Maex, Patrick van de Steeg, Ron Wilson: How Can System-Level Design Solve the Interconnect Technology Scaling Problem? DATE 2004: 332-339
10	EE	Jurjen Westra, Chris Bartels, Patrick Groeneveld: Probabilistic congestion prediction. ISPD 2004: 204-209
2003
9	EE	Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf: Nanometer design: place your bets. DAC 2003: 546-547
2002
8	EE	Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven: Tools or users: which is the bigger bottleneck? DAC 2002: 76-77
7	EE	Ralph H. J. M. Otten, Raul Camposano, Patrick Groeneveld: Design Automation for Deepsubmicron: Present and Future. DATE 2002: 650-659
6	EE	Patrick Groeneveld: Physical Design Challenges for Billion Transistor Chips. ICCD 2002: 78-83
2001
5	EE	Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni: Automatic Hierarchical Design: Fantasy or Reality? (Panel). ICCAD 2001: 656-
2000
4	EE	Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten: Timing closure: the solution and its problems. ASP-DAC 2000: 359-364
3	EE	Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer: Design closure (panel session): hope or hype? DAC 2000: 176-177
2	EE	Patrick Groeneveld, Jacob Greidinger, J. George Janac, Wilm E. Donath: The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only). ISPD 2000: 214
1990
1	EE	Patrick Groeneveld: A multiple layer contour-based gridless channel router. IEEE Trans. on CAD of Integrated Circuits and Systems 9(12): 1278-1288 (1990)

Coauthor Index

1	Charles J. Alpert	[12]
2	Chris Bartels	[10] [17]
3	Shekhar Y. Borkar (Shekhar Borkar)	[9]
4	Raul Camposano	[3] [4] [7]
5	Francky Catthoor	[11]
6	John M. Cohn	[9]
7	Ronald Collett	[8]
8	Olivier Coudert	[4] [5]
9	Andrea Cuomo	[11]
10	Antun Domic	[9]
11	Wilm E. Donath	[2]
12	Kees G. W. Goossens (Kees Goossens)	[17]
13	Jacob Greidinger	[2] [3]
14	Lambert van den Hoven	[8]
15	Jos Huisken	[17]
16	Michael Jackson	[3]
17	J. George Janac	[2]
18	Andrew B. Kahng	[8] [9]
19	Jürgen Koehl	[5]
20	Rudy Lauwereins	[11]
21	Lavi Lev	[8]
22	Karen Maex	[11]
23	Grant Martin	[11]
24	Jef L. van Meerbergen	[17]
25	Nancy Nettleton	[8]
26	Ralph H. J. M. Otten	[4] [7]
27	Scott Peterson	[5]
28	Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage)	[3]
29	Vivek Raghavan	[5]
30	Paul K. Rodman	[8]
31	Rob A. Rutenbar	[5]
32	Louis Scheffer	[3] [9] [16]
33	Jean-Pierre Schoellkopf	[9]
34	Naresh Soni	[5]
35	Patrick van de Steeg	[11]
36	Leon Stok	[4]
37	Jurjen Westra	[10] [13] [14] [15]
38	Ron Wilson	[11]