| 2008 |
|---|
| 16 | EE | Alexander Jesser,
Lars Hedrich:
A symbolic approach for mixed-signal model checking.
ASP-DAC 2008: 404-409 |
| 15 | EE | Sebastian Steinhorst,
Lars Hedrich:
Model Checking of Analog Systems using an Analog Specification Language.
DATE 2008: 324-329 |
| 14 | EE | Xiaoying Wang,
Lars Hedrich:
Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology.
DATE 2008: 800-803 |
| 2006 |
|---|
| 13 | EE | Xiaoying Wang,
Lars Hedrich:
An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis.
ASP-DAC 2006: 700-705 |
| 12 | EE | Xiaoying Wang,
Lars Hedrich:
Hierarchical exploration and selection of transistor-topologies for analog circuit design.
ISCAS 2006 |
| 11 | EE | Darius Grabowski,
Daniel Platte,
Lars Hedrich,
Erich Barke:
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms.
Electr. Notes Theor. Comput. Sci. 153(3): 37-52 (2006) |
| 2004 |
|---|
| 10 | EE | Lutz Näthke,
Volodymyr Burkhay,
Lars Hedrich,
Erich Barke:
Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques.
DATE 2004: 442-447 |
| 2002 |
|---|
| 9 | EE | Walter Hartong,
Lars Hedrich,
Erich Barke:
On Discrete Modeling and Model Checking for Nonlinear Analog Systems.
CAV 2002: 401-413 |
| 8 | EE | Walter Hartong,
Lars Hedrich,
Erich Barke:
Model checking algorithms for analog verification.
DAC 2002: 542-547 |
| 7 | EE | Walter Hartong,
Lars Hedrich,
Erich Barke:
An Approach to Model Checking for Nonlinear Analog Systems.
DATE 2002: 1080 |
| 6 | EE | Rolf Popp,
Joerg Oehmen,
Lars Hedrich,
Erich Barke:
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits.
DATE 2002: 274-278 |
| 5 | EE | Andreas C. Lemke,
Lars Hedrich,
Erich Barke:
Analog circuit sizing based on formal methods using affine arithmetic.
ICCAD 2002: 486-489 |
| 2000 |
|---|
| 4 | EE | Thorsten Adler,
Hiltrud Brocke,
Lars Hedrich,
Erich Barke:
A current driven routing and verification methodology for analog applications.
DAC 2000: 385-389 |
| 1998 |
|---|
| 3 | EE | Lars Hedrich,
Erich Barke:
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances.
DATE 1998: 649- |
| 1996 |
|---|
| 2 | EE | Carsten Borchers,
Lars Hedrich,
Erich Barke:
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits.
DAC 1996: 236-239 |
| 1995 |
|---|
| 1 | EE | Lars Hedrich,
Erich Barke:
A formal approach to nonlinear analog circuit verification.
ICCAD 1995: 123-127 |
