| 2009 |
|---|
| 181 | EE | Balasubramanian Sethuraman,
Ranga Vemuri:
A methodology for application-specific NoC architecture generation in a dynamic task structure environment.
ACM Great Lakes Symposium on VLSI 2009: 149-152 |
| 180 | EE | Almitra Pradhan,
Ranga Vemuri:
Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits.
VLSI Design 2009: 131-136 |
| 179 | EE | Shubhankar Basu,
Balaji Kommineni,
Ranga Vemuri:
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space.
VLSI Design 2009: 433-438 |
| 178 | EE | Angan Das,
Ranga Vemuri:
Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design.
VLSI Design 2009: 445-450 |
| 2008 |
|---|
| 177 | EE | Almitra Pradhan,
Ranga Vemuri:
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection.
ACM Great Lakes Symposium on VLSI 2008: 159-162 |
| 176 | EE | Angan Das,
Ranga Vemuri:
Topology synthesis of analog circuits based on adaptively generated building blocks.
DAC 2008: 44-49 |
| 175 | EE | Almitra Pradhan,
Ranga Vemuri:
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches.
DATE 2008: 523-526 |
| 174 | EE | Angan Das,
Ranga Vemuri:
A Self-learning Optimization Technique for Topology Design of Computer Networks.
EvoWorkshops 2008: 38-51 |
| 173 | EE | Hao Xu,
Wen-Ben Jone,
Ranga Vemuri:
Accurate energy breakeven time estimation for run-time power gating.
ICCAD 2008: 161-168 |
| 172 | EE | Hao Xu,
Ranga Vemuri,
Wen-Ben Jone:
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW.
ICCD 2008: 618-625 |
| 171 | EE | Angan Das,
Ranga Vemuri:
ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework.
ISCAS 2008: 2542-2545 |
| 170 | EE | Hao Xu,
Ranga Vemuri,
Wen-Ben Jone:
Dynamic virtual ground voltage estimation for power gating.
ISLPED 2008: 27-32 |
| 169 | EE | Shubhankar Basu,
Balaji Kommineni,
Ranga Vemuri:
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance.
ISQED 2008: 162-167 |
| 168 | EE | Shubhankar Basu,
Balaji Kommineni,
Ranga Vemuri:
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples.
VLSI Design 2008: 287-293 |
| 167 | EE | Almitra Pradhan,
Ranga Vemuri:
On the Use of Hash Tables for Efficient Analog Circuit Synthesis.
VLSI Design 2008: 647-652 |
| 166 | EE | Srividhya Rammohan,
Vijay Sundaresan,
Ranga Vemuri:
Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design.
VLSI Design 2008: 699-705 |
| 2007 |
|---|
| 165 | EE | Balasubramanian Sethuraman,
Ranga Vemuri:
Power variations of multi-port routers in an application-specific NoC design : A case study.
ICCD 2007: 595-600 |
| 164 | EE | Angan Das,
Ranga Vemuri:
GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis.
ISCAS 2007: 2702-2705 |
| 163 | EE | Balasubramanian Sethuraman,
Ranga Vemuri:
Multicasting based topology generation and core mapping for a power efficient networks-on-chip.
ISLPED 2007: 399-402 |
| 162 | EE | Shubhankar Basu,
Priyanka Thakore,
Ranga Vemuri:
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques.
ISQED 2007: 814-820 |
| 161 | EE | Angan Das,
Ranga Vemuri:
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms.
ISVLSI 2007: 145-152 |
| 160 | EE | Shubhankar Basu,
Ranga Vemuri:
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs.
ISVLSI 2007: 291-298 |
| 159 | EE | Huiying Yang,
Ranga Vemuri:
Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis.
VLSI Design 2007: 201-206 |
| 158 | EE | Balasubramanian Sethuraman,
Ranga Vemuri:
A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures.
VLSI Design 2007: 419-426 |
| 157 | EE | Vijay Sundaresan,
Srividhya Rammohan,
Ranga Vemuri:
Power invariant secure IC design methodology using reduced complementary dynamic and differential logic.
VLSI-SoC 2007: 1-6 |
| 156 | EE | Almitra Pradhan,
Ranga Vemuri:
Regression based circuit matrix models for accurate performance estimation of analog circuits.
VLSI-SoC 2007: 48-53 |
| 155 | EE | Raoul F. Badaoui,
Ranga Vemuri:
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis
CoRR abs/0710.4717: (2007) |
| 154 | EE | Jawad Khan,
Ranga Vemuri:
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms
CoRR abs/0710.4752: (2007) |
| 2006 |
|---|
| 153 | EE | Renqiu Huang,
Ranga Vemuri:
Transformation synthesis for data intensive applications to FPGAs.
ACM Great Lakes Symposium on VLSI 2006: 349-352 |
| 152 | EE | Huiying Yang,
Ranga Vemuri:
Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis.
DATE 2006: 283-284 |
| 151 | EE | Balasubramanian Sethuraman,
Ranga Vemuri:
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs.
DATE 2006: 947-952 |
| 150 | EE | Balasubramanian Sethuraman,
Ranga Vemuri:
Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip.
FPL 2006: 1-4 |
| 149 | EE | Xin Jia,
Ranga Vemuri:
Studying a GALS FPGA architecture using a parameterized automatic design flow.
ICCAD 2006: 688-693 |
| 148 | EE | Mukesh Ranjan,
Ranga Vemuri:
Exact hierarchical symbolic analysis of large analog networks using a general interconnection template.
ISCAS 2006 |
| 147 | EE | Vijay Sundaresan,
Ranga Vemuri:
A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning.
ISVLSI 2006: 323-328 |
| 146 | EE | Amitava Bhaduri,
Ranga Vemuri:
Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics.
VLSI Design 2006: 141-146 |
| 145 | EE | Xin Jia,
Ranga Vemuri:
CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture.
VLSI Design 2006: 251-256 |
| 144 | EE | Mengmeng Ding,
Ranga Vemuri:
Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition.
VLSI Design 2006: 553-556 |
| 143 | EE | Ritochit Chakraborty,
Mukesh Ranjan,
Ranga Vemuri:
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction.
VLSI Design 2006: 689-694 |
| 142 | EE | Nagu R. Dhanwada,
Alex Doboli,
Adrián Núñez-Aldana,
Ranga Vemuri:
Hierarchical constraint transformation based on genetic optimization for analog system synthesis.
Integration 39(3): 267-290 (2006) |
| 2005 |
|---|
| 141 | EE | Amitava Bhaduri,
Ranga Vemuri:
Moment-driven coupling-aware routing methodology.
ACM Great Lakes Symposium on VLSI 2005: 390-395 |
| 140 | EE | Balasubramanian Sethuraman,
Prasun Bhattacharya,
Jawad Khan,
Ranga Vemuri:
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip.
ACM Great Lakes Symposium on VLSI 2005: 452-457 |
| 139 | EE | Anuradha Agarwal,
Glenn Wolfe,
Ranga Vemuri:
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits.
ACM Great Lakes Symposium on VLSI 2005: 482-487 |
| 138 | EE | Xin Jia,
Ranga Vemuri:
Using GALS architecture to reduce the impact of long wire delay on FPGA performance.
ASP-DAC 2005: 1260-1263 |
| 137 | EE | Huiying Yang,
Mukesh Ranjan,
Wim Verhaegen,
Mengmeng Ding,
Ranga Vemuri,
Georges G. E. Gielen:
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams.
ASP-DAC 2005: 230-235 |
| 136 | EE | Mengmeng Ding,
Glenn Wolfe,
Ranga Vemuri:
An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels.
ASP-DAC 2005: 477-482 |
| 135 | EE | Mengmeng Ding,
Ranga Vemuri:
A combined feasibility and performance macromodel for analog circuits.
DAC 2005: 63-68 |
| 134 | EE | Mengmeng Ding,
Ranga Vemuri:
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling.
DATE 2005: 1088-1089 |
| 133 | EE | Raoul F. Badaoui,
Ranga Vemuri:
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis.
DATE 2005: 138-143 |
| 132 | EE | Jawad Khan,
Ranga Vemuri:
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms.
DATE 2005: 622-627 |
| 131 | EE | Amitava Bhaduri,
Ranga Vemuri:
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric.
DATE 2005: 922-923 |
| 130 | EE | Xin Jia,
Ranga Vemuri:
The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture.
FCCM 2005: 291-292 |
| 129 | | Xin Jia,
Ranga Vemuri:
A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation.
FPL 2005: 287-292 |
| 128 | | Jawad Khan,
Ranga Vemuri:
Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes.
FPL 2005: 543-546 |
| 127 | | Renqiu Huang,
Ranga Vemuri:
PAHLS: Towards Run-Time Synthesis for FPGAs.
FPL 2005: 739-740 |
| 126 | | Anuradha Agarwal,
Ranga Vemuri:
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits.
ICCAD 2005: 430-436 |
| 125 | EE | Anuradha Agarwal,
Ranga Vemuri:
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners.
ICCD 2005: 444-452 |
| 124 | EE | Jawad Khan,
Ranga Vemuri:
Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units.
IPDPS 2005 |
| 123 | EE | Raoul F. Badaoui,
Ranga Vemuri:
Analog VLSI circuit-level synthesis using multi-placement structures.
ISCAS (6) 2005: 5978-5981 |
| 122 | EE | Renqiu Huang,
Ranga Vemuri:
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs.
ISVLSI 2005: 250-251 |
| 121 | EE | Huiying Yang,
Anuradha Agarwal,
Ranga Vemuri:
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams.
ISVLSI 2005: 71-76 |
| 120 | EE | Mengmeng Ding,
Ranga Vemuri:
An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification.
VLSI Design 2005: 528-534 |
| 119 | EE | Madhubanti Mukherjee,
Ranga Vemuri:
On Physical-Aware Synthesis of Vertically Integrated 3D Systems.
VLSI Design 2005: 647-652 |
| 118 | EE | Renqiu Huang,
Ranga Vemuri:
On-Line Synthesis for Partially Reconfigurable FPGAs.
VLSI Design 2005: 663-668 |
| 117 | EE | Manish Handa,
Ranga Vemuri:
Hardware assisted two dimensional ultra fast online placement.
IJES 1(3/4): 291-299 (2005) |
| 2004 |
|---|
| 116 | EE | Raoul F. Badaoui,
Hemanth Sampath,
Anuradha Agarwal,
Ranga Vemuri:
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis.
ACM Great Lakes Symposium on VLSI 2004: 271-276 |
| 115 | EE | Anuradha Agarwal,
Hemanth Sampath,
Veena Yelamanchili,
Ranga Vemuri:
Fast and accurate parasitic capacitance models for layout-aware.
DAC 2004: 145-150 |
| 114 | EE | Manish Handa,
Ranga Vemuri:
An efficient algorithm for finding empty space for online FPGA placement.
DAC 2004: 960-965 |
| 113 | EE | Anuradha Agarwal,
Hemanth Sampath,
Veena Yelamanchili,
Ranga Vemuri:
Accurate Estimation of Parasitic Capacitances in Analog Circuits.
DATE 2004: 1364-1365 |
| 112 | EE | Mukesh Ranjan,
Wim Verhaegen,
Anuradha Agarwal,
Hemanth Sampath,
Ranga Vemuri,
Georges G. E. Gielen:
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.
DATE 2004: 604-609 |
| 111 | EE | Manish Handa,
Ranga Vemuri:
A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement.
DATE 2004: 744-745 |
| 110 | | Jawad Khan,
Jayanthi Rajagopalan,
Renqiu Huang,
Ranga Vemuri:
A Portable Face Recognition System Using Reconfigurable Hardware.
ERSA 2004: 213-217 |
| 109 | | Jawad Khan,
Balasubramanian Sethuraman,
Ranga Vemuri:
A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms.
ERSA 2004: 33-37 |
| 108 | | Manish Handa,
Ranga Vemuri:
Area Fragmentation in Reconfigurable Operating Systems.
ERSA 2004: 77-83 |
| 107 | | Xin Jia,
Ranga Vemuri:
A Design Methodology for Self-Timed Event Logic Pipelines.
ESA/VLSI 2004: 475-479 |
| 106 | EE | Manish Handa,
Ranga Vemuri:
An Integrated Online Scheduling and Placement Methodology.
FPL 2004: 444-453 |
| 105 | EE | Jawad Khan,
Ranga Vemuri:
An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms.
FPL 2004: 669-678 |
| 104 | EE | Xin Jia,
Jayanthi Rajagopalan,
Ranga Vemuri:
A Dynamically Reconfigurable Asynchronous FPGA Architecture.
FPL 2004: 836-841 |
| 103 | EE | Renqiu Huang,
Manish Handa,
Ranga Vemuri:
Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs.
FPL 2004: 900-905 |
| 102 | EE | Renqiu Huang,
Ranga Vemuri:
Analysis and evaluation of a hybrid interconnect structure for FPGAs.
ICCAD 2004: 595-601 |
| 101 | EE | Ranga Vemuri,
Glenn Wolfe:
Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines.
ICCAD 2004: 931-938 |
| 100 | EE | Madhubanti Mukherjee,
Ranga Vemuri:
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems.
ICCD 2004: 222-227 |
| 99 | EE | Renqiu Huang,
Ranga Vemuri:
Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs.
IPDPS 2004 |
| 98 | EE | Manish Handa,
Ranga Vemuri:
Hardware Assisted Two Dimensional Ultra Fast Placement.
IPDPS 2004 |
| 97 | EE | Alex Doboli,
Nagu R. Dhanwada,
Adrián Núñez-Aldana,
Ranga Vemuri:
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications.
ACM Trans. Design Autom. Electr. Syst. 9(2): 238-271 (2004) |
| 2003 |
|---|
| 96 | EE | Madhubanti Mukherjee,
Ranga Vemuri:
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits.
ICCD 2003: 436-440 |
| 95 | EE | Manish Handa,
Rajesh Radhakrishnan,
Madhubanti Mukherjee,
Ranga Vemuri:
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs.
VLSI Design 2003: 91- |
| 94 | | Glenn Wolfe,
Mengmeng Ding,
Ranga Vemuri:
Adaptive Sampling and Modeling of Analog Circuit Performance Parameters.
VLSI-SOC 2003: 142- |
| 93 | | Hemanth Sampath,
Ranga Vemuri:
MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators.
VLSI-SOC 2003: 416-421 |
| 92 | EE | Alex Doboli,
Ranga Vemuri:
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1504-1520 (2003) |
| 91 | EE | Alex Doboli,
Ranga Vemuri:
Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1556-1568 (2003) |
| 90 | EE | Glenn Wolfe,
Ranga Vemuri:
Extraction and use of neural network models in automated synthesis of operational amplifiers.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(2): 198-212 (2003) |
| 2002 |
|---|
| 89 | EE | Alex Doboli,
Ranga Vemuri:
A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems.
DATE 2002: 760-769 |
| 88 | EE | Jawad Khan,
Manish Handa,
Ranga Vemuri:
iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications.
FPL 2002: 69-78 |
| 87 | EE | Srinivasan Dasasathyan,
Rajesh Radhakrishnan,
Ranga Vemuri:
Framework for Synthesis of Virtual Pipelines.
VLSI Design 2002: 326-331 |
| 86 | EE | Ranga Vemuri,
Srinivas Katkoori,
Meenakshi Kaul,
Jay Roy:
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.
ACM Trans. Design Autom. Electr. Syst. 7(1): 189-216 (2002) |
| 85 | EE | Karam S. Chatha,
Ranga Vemuri:
Hardware-software partitioning and pipelined scheduling of transformative applications.
IEEE Trans. VLSI Syst. 10(3): 193-208 (2002) |
| 2001 |
|---|
| 84 | EE | Sree Ganesan,
Ranga Vemuri:
Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems.
ARVLSI 2001: 172-187 |
| 83 | EE | Rajesh Radhakrishnan,
Elena Teica,
Ranga Vemuri:
Verification of Basic Block Schedules Using RTL Transformations.
CHARME 2001: 173-178 |
| 82 | EE | Karam S. Chatha,
Ranga Vemuri:
MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs.
CODES 2001: 42-47 |
| 81 | EE | Sree Ganesan,
Ranga Vemuri:
Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems.
DAC 2001: 133-138 |
| 80 | EE | Alex Doboli,
Ranga Vemuri:
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints.
DAC 2001: 629-634 |
| 79 | EE | Iyad Ouaiss,
Ranga Vemuri:
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers.
DATE 2001: 650-657 |
| 78 | EE | Elena Teica,
Rajesh Radhakrishnan,
Ranga Vemuri:
On the verification of synthesized designs using automatically generated transformational witnesses.
DATE 2001: 798 |
| 77 | EE | Alex Doboli,
Ranga Vemuri:
A regularity-based hierarchical symbolic analysis method for large-scale analog networks.
DATE 2001: 806 |
| 76 | EE | Amit Kasat,
Iyad Ouaiss,
Ranga Vemuri:
Memory Synthesis for FPGA-Based Reconfigurable Computers.
FPL 2001: 70-80 |
| 75 | | Yi Pan,
Jie Li,
Ranga Vemuri:
Continous Wavelet Transform on Reconfigurable Meshes.
IPDPS 2001: 114 |
| 74 | | Iyad Ouaiss,
Ranga Vemuri:
Global memory mapping for FPGA-based reconfigurable systems.
IPDPS 2001: 144 |
| 73 | EE | S. Saha,
Ranga Vemuri:
Use of adaptive integer-to-integer wavelet transforms in lossless image coding.
ISCAS (2) 2001: 393-396 |
| 72 | EE | Alex Doboli,
Ranga Vemuri:
Hierarchical performance optimization for synthesis of linear analog systems.
ISCAS (5) 2001: 431-434 |
| 71 | EE | Sree Ganesan,
Ranga Vemuri:
Library Binding for High-Level Synthesis of Analog Systems.
VLSI Design 2001: 261-268 |
| 70 | EE | Sujatha Sundararaman,
Sriram Govindarajan,
Ranga Vemuri:
Application Specific Macro Based Synthesis.
VLSI Design 2001: 317- |
| 69 | | Naren Narasimhan,
Elena Teica,
Rajesh Radhakrishnan,
Sriram Govindarajan,
Ranga Vemuri:
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis.
Formal Methods in System Design 19(3): 237-273 (2001) |
| 2000 |
|---|
| 68 | EE | Satish Ganesan,
Ranga Vemuri:
An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement.
DATE 2000: 320-325 |
| 67 | EE | Iyad Ouaiss,
Ranga Vemuri:
Efficient Resource Arbitration in Reconfigurable Computing Environments.
DATE 2000: 560-566 |
| 66 | EE | Sree Ganesan,
Ranga Vemuri:
Technology Mapping and Retargeting for Field-Programmable Analog Arrays.
DATE 2000: 58- |
| 65 | EE | Sriram Govindarajan,
Ranga Vemuri:
Improving the Schedule Quality of Static-List Time-Constrained Scheduling.
DATE 2000: 749 |
| 64 | EE | Sriram Govindarajan,
Ranga Vemuri:
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS.
FPL 2000: 7-18 |
| 63 | EE | Preetham Lakshmikanthan,
Sriram Govindarajan,
Vinoo Srinivasan,
Ranga Vemuri:
Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints.
IPDPS Workshops 2000: 924-931 |
| 62 | EE | Sriram Govindarajan,
Vinoo Srinivasan,
Preetham Lakshmikanthan,
Ranga Vemuri:
A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures.
VLSI Design 2000: 212-219 |
| 61 | EE | Abhijit Ghosh,
Ranga Vemuri:
Formal Verification of Synthesized Mixed Signal Designs Using *BMDs.
VLSI Design 2000: 84- |
| 60 | | Nazanin Mansouri,
Ranga Vemuri:
Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs.
Formal Methods in System Design 16(1): 59-91 (2000) |
| 59 | | Ranga Vemuri,
Randolph E. Harr:
Configurable Computing: Technology and Applications - Guest Editors' Introduction.
IEEE Computer 33(4): 39-40 (2000) |
| 58 | EE | Meenakshi Kaul,
Ranga Vemuri:
Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems.
VLSI Signal Processing 24(2-3): 181-209 (2000) |
| 1999 |
|---|
| 57 | EE | Nagu R. Dhanwada,
Adrián Núñez-Aldana,
Ranga Vemuri:
Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis.
ASP-DAC 1999: 153-156 |
| 56 | EE | Meenakshi Kaul,
Ranga Vemuri,
Sriram Govindarajan,
Iyad Ouaiss:
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications.
DAC 1999: 616-622 |
| 55 | EE | Alex Doboli,
Adrián Núñez-Aldana,
Nagu R. Dhanwada,
Sree Ganesan,
Ranga Vemuri:
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration.
DAC 1999: 951-957 |
| 54 | EE | Meenakshi Kaul,
Ranga Vemuri:
Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs.
DATE 1999: 202-209 |
| 53 | EE | Nazanin Mansouri,
Ranga Vemuri:
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs.
DATE 1999: 223- |
| 52 | EE | Nagu R. Dhanwada,
Adrián Núñez-Aldana,
Ranga Vemuri:
Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis.
DATE 1999: 328- |
| 51 | EE | Alex Doboli,
Ranga Vemuri:
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems.
DATE 1999: 338-345 |
| 50 | EE | Adrián Núñez-Aldana,
Ranga Vemuri:
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis.
DATE 1999: 406-411 |
| 49 | EE | Vinoo Srinivasan,
Ranga Vemuri:
Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures.
FCCM 1999: 272- |
| 48 | EE | Vinoo Srinivasan,
Ranga Vemuri:
Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures.
FPGA 1999: 253 |
| 47 | | Karam S. Chatha,
Ranga Vemuri:
Hardware-Software Codesign for Dynamically Reconfigurable Architectures.
FPL 1999: 175-184 |
| 46 | EE | Abhijit Ghosh,
Sandeep K. Lodha,
Ranga Vemuri:
Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops.
Great Lakes Symposium on VLSI 1999: 140-143 |
| 45 | EE | Srinivas Katkoori,
Ranga Vemuri:
Accurate Resource Estimation Algorithms for Behavioral Synthesis.
Great Lakes Symposium on VLSI 1999: 338-339 |
| 44 | EE | Abhijit Ghosh,
Ranga Vemuri:
Formal Verification of Synthesized Analog Designs.
ICCD 1999: 40-45 |
| 43 | EE | Sree Ganesan,
Ranga Vemuri:
A Methodology for Rapid Prototyping of Analog Systems.
ICCD 1999: 482-488 |
| 42 | EE | Karam S. Chatha,
Ranga Vemuri:
An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems.
IEEE International Workshop on Rapid System Prototyping 1999: 134-139 |
| 41 | | Vinoo Srinivasan,
Shankar Radhakrishnan,
Ranga Vemuri,
Jeffrey Walrath:
Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures.
IPPS/SPDP Workshops 1999: 588-596 |
| 40 | | Meenakshi Kaul,
Ranga Vemuri:
Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures.
IPPS/SPDP Workshops 1999: 606-615 |
| 39 | EE | Nagu R. Dhanwada,
Adrián Núñez-Aldana,
Ranga Vemuri:
A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis.
ISCAS (6) 1999: 362-365 |
| 38 | | Alex Doboli,
Ranga Vemuri:
A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications.
VLSI 1999: 305-317 |
| 37 | | Adrián Núñez-Aldana,
Ranga Vemuri:
A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements.
VLSI 1999: 318-32 |
| 36 | | Sree Ganesan,
Ranga Vemuri:
FAAR: A Router for Field-Programmable Analog Arrays.
VLSI Design 1999: 556-563 |
| 35 | | Nagu R. Dhanwada,
Adrián Núñez-Aldana,
Ranga Vemuri:
Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis.
VLSI Design 1999: 589-596 |
| 1998 |
|---|
| 34 | EE | Karam S. Chatha,
Ranga Vemuri:
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns.
CODES 1998: 139-143 |
| 33 | EE | Vinoo Srinivasan,
Shankar Radhakrishnan,
Ranga Vemuri:
Hardware Software Partitioning with Integrated Hardware Design Space Exploration.
DATE 1998: 28-35 |
| 32 | EE | Meenakshi Kaul,
Ranga Vemuri:
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures.
DATE 1998: 389- |
| 31 | EE | Sriram Govindarajan,
Iyad Ouaiss,
Meenakshi Kaul,
Vinoo Srinivasan,
Ranga Vemuri:
An Effective Design System for Dynamically Reconfigurable Architectures.
FCCM 1998: 312-313 |
| 30 | EE | Nazanin Mansouri,
Ranga Vemuri:
A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool.
FMCAD 1998: 204-221 |
| 29 | | Jeffrey Walrath,
Ranga Vemuri:
A Performance Modeling and Analysis Environment for Reconfigurable Computers.
IPPS/SPDP Workshops 1998: 19-24 |
| 28 | | Iyad Ouaiss,
Sriram Govindarajan,
Vinoo Srinivasan,
Meenakshi Kaul,
Ranga Vemuri:
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures.
IPPS/SPDP Workshops 1998: 31-36 |
| 27 | EE | Karam S. Chatha,
Ranga Vemuri:
A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems.
ISSS 1998: 145-151 |
| 26 | EE | Karam S. Chatha,
Ranga Vemuri:
Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns.
International Workshop on Rapid System Prototyping 1998: 218-224 |
| 25 | | Naren Narasimhan,
Ranga Vemuri:
On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System.
TPHOLs 1998: 367-386 |
| 24 | EE | Nagu R. Dhanwada,
Ranga Vemuri:
Constraint Allocation in Analog System Synthesis.
VLSI Design 1998: 253-258 |
| 23 | EE | Vinoo Srinivasan,
Ranga Vemuri:
A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining.
VLSI Design 1998: 435-441 |
| 1997 |
|---|
| 22 | EE | Jeffrey Walrath,
Ranga Vemuri:
Symbolic Evaluation of Performance Models for Tradeoff Visualization.
DAC 1997: 359-364 |
| 21 | EE | Sriram Govindarajan,
Ranga Vemuri:
Cone-based clustering heuristic for list-scheduling algorithms.
ED&TC 1997: 456-462 |
| 20 | EE | Jeffrey Walrath,
Ranga Vemuri,
W. Bradley:
Performance verification using partial evaluation and interval analysis.
ED&TC 1997: 622 |
| 19 | | Sriram Govindarajan,
Ranga Vemuri:
Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms.
ICCD 1997: 752-757 |
| 18 | EE | Madhavi Vootukuru,
Ranga Vemuri,
Nand Kumar:
Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs.
VLSI Design 1997: 140-145 |
| 1996 |
|---|
| 17 | EE | Naren Narasimhan,
Vinoo Srinivasan,
Madhavi Vootukuru,
Jeffrey Walrath,
Sriram Govindarajan,
Ranga Vemuri:
Rapid Prototyping of Reconfigurable Coprocessors.
ASAP 1996: 303-312 |
| 16 | | Naren Narasimhan,
Ranga Vemuri:
Specification of Control Flow Properties for Verification of Synthesized VHDL Designs.
FMCAD 1996: 327-345 |
| 15 | EE | Srinivas Katkoori,
Ranga Vemuri:
Simulation based architectural power estimation for PLA-based controllers.
ISLPED 1996: 121-124 |
| 14 | EE | Srinivas Katkoori,
Ranga Vemuri,
Jay Roy:
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis.
VLSI Design 1996: 126-132 |
| 13 | EE | Naren Narasimhan,
Ranga Vemuri,
Jay Roy:
Synchronous Controller Models for Synthesis from Communicating VHDL Processes.
VLSI Design 1996: 198-204 |
| 12 | | Ranga Vemuri,
Ram Manday,
Vijay Meduri:
Performance Modeling Using PDL.
IEEE Computer 29(4): 44-53 (1996) |
| 1995 |
|---|
| 11 | EE | Srinivas Katkoori,
Nand Kumar,
Ranga Vemuri:
High level profiling based low power synthesis technique.
ICCD 1995: 446- |
| 10 | EE | William L. Bradley,
Ranga Vemuri:
Transformations for functional verification of synthesized designs.
VLSI Design 1995: 243-248 |
| 9 | EE | Nand Kumar,
Srinivas Katkoori,
Leo Rader,
Ranga Vemuri:
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems.
IEEE Design & Test of Computers 12(3): 70-84 (1995) |
| 1993 |
|---|
| 8 | | Ram Mandayam,
Ranga Vemuri:
Performance Specification and Measurement.
CHDL 1993: 281-298 |
| 7 | EE | Ranga Vemuri,
Paddy Mamtora,
Praveen Sinha,
Nand Kumar,
Jayanta Roy,
Raghu Vutukuru:
Experiences in Functional Validation of a High Level Synthesis System.
DAC 1993: 194-201 |
| 6 | EE | Ram Mandayam,
Ranga Vemuri:
Performance Specification Using Attributed Grammars.
DAC 1993: 661-667 |
| 5 | | Ranga Vemuri,
Nand Kumar,
Raghu Vutukuru,
Prasad Subba Rao,
Praveen Sinha,
Ning Ren,
Paddy Mamtora,
Ram Mandayam,
Ram Vemuri,
Jayanta Roy:
An Integrated Multicomponent Synthesis for MCMs.
IEEE Computer 26(4): 62-74 (1993) |
| 1992 |
|---|
| 4 | EE | Rajiv Dutta,
Jayanta Roy,
Ranga Vemuri:
Distributed Design-Space Exploration for High-Level Synthesis Systems.
DAC 1992: 644-650 |
| 3 | EE | Jayanta Roy,
Nand Kumar,
Rajiv Dutta,
Ranga Vemuri:
DSS: A Distributed High-Level Synthesis System.
IEEE Design & Test of Computers 9(2): 18-32 (1992) |
| 1991 |
|---|
| 2 | | Ranga Vemuri,
Anuradha Sridhar:
Temporal Precondition Verification of Design Transformations.
CAV 1991: 125-135 |
| 1990 |
|---|
| 1 | EE | Ranga Vemuri:
On the notion of the normal form register-level structures and its applications in design-space exploration.
EURO-DAC 1990: 46-51 |
