| 2008 |
|---|
| 159 | EE | Matthias Krause,
Dominik Englert,
Oliver Bringmann,
Wolfgang Rosenstiel:
Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation.
CODES+ISSS 2008: 143-148 |
| 158 | EE | Jürgen Schnerr,
Oliver Bringmann,
Alexander Viehl,
Wolfgang Rosenstiel:
High-performance timing simulation of embedded software.
DAC 2008: 290-295 |
| 157 | EE | Djones Lettnin,
Pradeep Kumar Nalla,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel,
Tobias Kirsten,
Volker Schonknecht,
Stephan Reitemeyer:
Verification of Temporal Properties in Automotive Embedded Software.
DATE 2008: 164-169 |
| 156 | EE | Dominik Brugger,
Sergejus Butovas,
Martin Bogdan,
Cornelius Schwarz,
Wolfgang Rosenstiel:
Direct and inverse solution for a stimulus adaptation problem using SVR.
ESANN 2008: 397-402 |
| 155 | EE | Alexander Viehl,
Björn Sander,
Oliver Bringmann,
Wolfgang Rosenstiel:
Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties.
FDL 2008: 105-110 |
| 154 | EE | Christian Kerstan,
Nico Bannow,
Wolfgang Rosenstiel:
Enabling Automated Code Transformation and Variable Tracing.
FDL 2008: 209-214 |
| 153 | EE | Sven Eisenhardt,
Thomas Schweizer,
Julio A. de Oliveira Filho,
Tobias Oppold,
Wolfgang Rosenstiel,
Alexander Thomas,
Jürgen Becker,
Frank Hannig,
Dmitrij Kissler,
Hritam Dutta,
Jürgen Teich,
Heiko Hinkelmann,
Peter Zipf,
Manfred Glesner:
Coarse-grained reconfiguration.
FPL 2008: 349 |
| 152 | | Andreas Bernauer,
Dirk Fritz,
Wolfgang Rosenstiel:
Evaluation of the Learning Classifier System XCS for SoC run-time control.
GI Jahrestagung (2) 2008: 763-770 |
| 151 | EE | Patrick Heckeler,
Marcus Ritt,
Jörg Behrend,
Wolfgang Rosenstiel:
Object-Oriented Message-Passing in Heterogeneous Environments.
PVM/MPI 2008: 151-158 |
| 150 | EE | Julio A. de Oliveira Filho,
Ana Bunoza,
Jürgen Sommer,
Wolfgang Rosenstiel:
Self-Localization in a Low Cost Bluetooth Environment.
UIC 2008: 258-270 |
| 2007 |
|---|
| 149 | EE | Axel Siebenborn,
Alexander Viehl,
Oliver Bringmann,
Wolfgang Rosenstiel:
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes.
ASP-DAC 2007: 32-37 |
| 148 | EE | Alexander Viehl,
Markus Schwarz,
Oliver Bringmann,
Wolfgang Rosenstiel:
Probabilistic performance risk analysis at system-level.
CODES+ISSS 2007: 185-190 |
| 147 | EE | Matthias Krause,
Oliver Bringmann,
André Hergenhan,
Gökhan Tabanoglu,
Wolfgang Rosenstiel:
Timing simulation of interconnected AUTOSAR software-components.
DATE 2007: 474-479 |
| 146 | EE | Timo Schönwald,
Jochen Zimmermann,
Oliver Bringmann,
Wolfgang Rosenstiel:
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures.
DSD 2007: 527-534 |
| 145 | EE | Pradeep Kumar Nalla,
Jörg Behrend,
Prakash Mohan Peranandam,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Grid Based Fast Falsification For Bounded Property Checking.
FDL 2007: 299-304 |
| 144 | | Michael Bensch,
Dominik Brugger,
Wolfgang Rosenstiel,
Martin Bogdan,
Wilhelm G. Spruth,
Peter Baeuerle:
Self-Learning Prediction System for Optimisation of Workload Management in a Mainframe Operating System.
ICEIS (2) 2007: 212-218 |
| 143 | EE | Alexander Viehl,
Markus Schwarz,
Oliver Bringmann,
Wolfgang Rosenstiel:
A Hybrid Approach for System-Level Design Evaluation.
IESS 2007: 165-178 |
| 142 | EE | Tobias Oppold,
Sven Eisenhardt,
Wolfgang Rosenstiel:
Optimization of Area and Performance by Processor-Like Reconfiguration.
IPDPS 2007: 1-8 |
| 141 | EE | Djones Lettnin,
Markus Winterholer,
Axel G. Braun,
Joachim Gerlach,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Coverage Driven Verification applied to Embedded Software.
ISVLSI 2007: 159-164 |
| 140 | EE | Jürgen Schnerr,
Oliver Bringmann,
Wolfgang Rosenstiel:
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
CoRR abs/0710.4644: (2007) |
| 139 | EE | Tobias Oppold,
Thomas Schweizer,
Julio A. de Oliveira Filho,
Sven Eisenhardt,
Wolfgang Rosenstiel:
CRC - Concepts and Evaluation of Processor-Like Reconfigurable Architectures (CRC - Konzepte und Bewertung prozessorartig rekonfigurierbarer Architekturen).
it - Information Technology 49(3): 157- (2007) |
| 2006 |
|---|
| 138 | EE | Abdelmajid Bouajila,
Andreas Bernauer,
Andreas Herkersdorf,
Wolfgang Rosenstiel,
Oliver Bringmann,
Walter Stechele:
Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs.
BICC 2006: 107-113 |
| 137 | EE | Prakash Mohan Peranandam,
Pradeep Kumar Nalla,
Jürgen Ruf,
Roland J. Weiss,
Thomas Kropf,
Wolfgang Rosenstiel:
Fast falsification based on symbolic bounded property checking.
DAC 2006: 1077-1082 |
| 136 | EE | Alexander Viehl,
Timo Schönwald,
Oliver Bringmann,
Wolfgang Rosenstiel:
Formal performance analysis and simulation of UML/SysML models for ESL design.
DATE 2006: 242-247 |
| 135 | EE | Nico Bannow,
Karsten Haug,
Wolfgang Rosenstiel:
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives.
DATE Designers' Forum 2006: 217-218 |
| 134 | EE | Jan-Hendrik Oetjens,
Joachim Gerlach,
Wolfgang Rosenstiel:
Flexible specification and application of rule-based transformations in an automotive design flow.
DATE Designers' Forum 2006: 82-87 |
| 133 | EE | Janina A. Brenner,
Jan van der Veen,
Sándor P. Fekete,
Julio A. de Oliveira Filho,
Wolfgang Rosenstiel:
Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures.
FPL 2006: 1-6 |
| 132 | | Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel,
Abdelmajid Bouajila,
Walter Stechele,
Andreas Herkersdorf:
An Architecture for Runtime Evaluation of SoC Reliability.
GI Jahrestagung (1) 2006: 177- |
| 131 | EE | Abdelmajid Bouajila,
Johannes Zeppenfeld,
Walter Stechele,
Andreas Herkersdorf,
Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel:
Organic Computing at the System on Chip Level.
VLSI-SoC 2006: 338-341 |
| 130 | EE | Pradeep Kumar Nalla,
Roland J. Weiss,
Prakash Mohan Peranandam,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Distributed Symbolic Bounded Property Checking.
Electr. Notes Theor. Comput. Sci. 135(2): 47-63 (2006) |
| 2005 |
|---|
| 129 | | Gabriel Lipsa,
Andreas Herkersdorf,
Wolfgang Rosenstiel,
Oliver Bringmann,
Walter Stechele:
Towards a Framework and a Design Methodology for Autonomous SoC.
ARCS Workshops 2005: 101-108 |
| 128 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Axel Siebenborn:
Conflict analysis in multiprocess synthesis for optimized system integration.
CODES+ISSS 2005: 15-20 |
| 127 | EE | Jürgen Schnerr,
Oliver Bringmann,
Wolfgang Rosenstiel:
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs.
DATE 2005: 792-797 |
| 126 | | Wolfgang Rosenstiel,
Reinaldo A. Bergamaschi,
Frank Ghenassia,
Thorsten Groetker,
Masamichi Kawarabayashi,
Marinus C. van Lier,
Albrecht Mayer,
Mike Meredith,
Mark Milligan,
Stuart Swan:
Is there a Market for SystemC Tools?
DATE 2005: 950 |
| 125 | EE | Michael Bensch,
Michael Schröder,
Martin Bogdan,
Wolfgang Rosenstiel:
Feature selection for high-dimensional industrial data.
ESANN 2005: 375-380 |
| 124 | EE | Sven Ganzenmüller,
Simon Pinkenburg,
Wolfgang Rosenstiel:
SPH2000: A Parallel Object-Oriented Framework for Particle Simulations with SPH.
Euro-Par 2005: 1275-1284 |
| 123 | EE | Luis Avila,
Rolando Dölling,
Thomas Ifström,
Peter Jores,
Wolfgang Rosenstiel:
Toward seamless top-down of A/MS systems.
FDL 2005: 165-172 |
| 122 | EE | Axel Braun,
Joachim Gerlach,
Wolfgang Rosenstiel,
Axel Siebenborn,
Oliver Bringmann:
SystemC-Based Communication and Performance Analysis.
FDL 2005: 33-48 |
| 121 | EE | Roland J. Weiss,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Efficient and Customizable Integration of Temporal Properties.
FDL 2005: 385-397 |
| 120 | | Tobias Oppold,
Thomas Schweizer,
Tommy Kuhn,
Wolfgang Rosenstiel,
Urs Kanus,
Wolfgang Straßer:
Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures.
FPL 2005: 185-190 |
| 119 | EE | Gabriel Lipsa,
Andreas Herkersdorf,
Wolfgang Rosenstiel,
Oliver Bringmann,
Walter Stechele:
Towards a Framework and a Design Methodology for Autonomic SoC.
ICAC 2005: 391-392 |
| 118 | EE | Thomas Hermle,
Martin Bogdan,
Cornelius Schwarz,
Wolfgang Rosenstiel:
ANN-Based System for Sorting Spike Waveforms Employing Refractory Periods.
ICANN (1) 2005: 121-126 |
| 117 | EE | Thomas Navin Lal,
Michael Schröder,
N. Jeremy Hill,
Hubert Preißl,
Thilo Hinterberger,
Jürgen Mellinger,
Martin Bogdan,
Wolfgang Rosenstiel,
Thomas Hofmann,
Niels Birbaumer,
Bernhard Schölkopf:
A brain computer interface with online feedback based on magnetoencephalography.
ICML 2005: 465-472 |
| 116 | | Jun Qin,
Simon Pinkenburg,
Wolfgang Rosenstiel:
Parallel Motif Search using ParSeq.
Parallel and Distributed Computing and Networks 2005: 601-607 |
| 2004 |
|---|
| 115 | EE | C. Schulz-Key,
Markus Winterholer,
Thomas Schweizer,
Tommy Kuhn,
Wolfgang Rosenstiel:
Object-oriented modeling and synthesis of SystemC specifications.
ASP-DAC 2004: 238-243 |
| 114 | EE | Donatella Sciuto,
Grant Martin,
Wolfgang Rosenstiel,
Stuart Swan,
Frank Ghenassia,
Peter Flake,
Johny Srouji:
SystemC and SystemVerilog: Where do They Fit? Where are They Going?
DATE 2004: 122-129 |
| 113 | EE | Djones Lettnin,
Axel G. Braun,
Martin Bogdan,
Joachim Gerlach,
Wolfgang Rosenstiel:
Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks.
DATE 2004: 248-255 |
| 112 | EE | Axel Siebenborn,
Oliver Bringmann,
Wolfgang Rosenstiel:
Communication Analysis for System-On-Chip Design.
DATE 2004: 648-655 |
| 111 | EE | Stephen Schmitt,
Wolfgang Rosenstiel:
Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments.
DATE 2004: 96-101 |
| 110 | EE | Andreas Vörg,
Martin Radetzki,
Wolfgang Rosenstiel:
Measurement of IP Qualification Costs and Benefits.
DATE 2004: 996-1001 |
| 109 | EE | M. Hipp,
Wolfgang Rosenstiel:
Parallel Hybrid Particle Simulations Using MPI and OpenMP.
Euro-Par 2004: 189-197 |
| 108 | EE | Nico Bannow,
Karsten Haug,
Wolfgang Rosenstiel:
Performance Analysis and Automated C++ Modularization Using Module-Adapters for SystemC.
FDL 2004: 416-428 |
| 107 | | Andreas Herkersdorf,
Wolfgang Rosenstiel:
Towards a Framework and a Design Methodology for Autonomic Integrated Systems.
GI Jahrestagung (2) 2004: 610-615 |
| 106 | EE | Thomas Navin Lal,
Thilo Hinterberger,
Guido Widman,
Michael Schröder,
N. Jeremy Hill,
Wolfgang Rosenstiel,
Christian Erich Elger,
Bernhard Schölkopf,
Niels Birbaumer:
Methods Towards Invasive Human Brain Computer Interfaces.
NIPS 2004 |
| 105 | EE | Tobias Oppold,
Thomas Schweizer,
Tommy Kuhn,
Wolfgang Rosenstiel:
A Design Environment for Processor-Like Reconfigurable Hardware.
PARELEC 2004: 171-176 |
| 104 | EE | Axel Siebenborn,
Oliver Bringmann,
Wolfgang Rosenstiel:
Communication Analysis for Network-on-Chip Design.
PARELEC 2004: 315-320 |
| 103 | EE | Simon Pinkenburg,
Wolfgang Rosenstiel:
Parallel I/O in an Object-Oriented Message-Passing Library.
PVM/MPI 2004: 251-258 |
| 102 | EE | Jürgen Ruf,
Roland J. Weiss,
Thomas Kropf,
Wolfgang Rosenstiel:
Modeling and Formal Verification of Production Automation Systems.
SoftSpez Final Report 2004: 541-566 |
| 101 | EE | Klaus Beschorner,
Wolfgang Rosenstiel,
Wilhelm G. Spruth:
Untersuchungen zur effizienten Kommunikation in EJB-Systemen.
Inform., Forsch. Entwickl. 18(2): 68-79 (2004) |
| 100 | EE | Wolfgang Rosenstiel:
IP and design reuse.
Integration 37(4): 191-192 (2004) |
| 99 | EE | Andreas Vörg,
Wolfgang Rosenstiel:
Automation of IP qualification and IP exchange.
Integration 37(4): 323-352 (2004) |
| 2003 |
|---|
| 98 | EE | Wolfgang Rosenstiel,
Rudy Lauwereins,
Ivo Bolsens,
Chris Rowen,
Yankin Tanurhan,
Kees A. Vissers,
S. Wang:
Panel Title: Reconfigurable Computing - Different Perspectives.
DATE 2003: 10476-10477 |
| 97 | EE | Jürgen Schnerr,
Gunter Haug,
Wolfgang Rosenstiel:
Instruction Set Emulation for Rapid Prototyping of SoCs .
DATE 2003: 10562-10569 |
| 96 | EE | Martin Bogdan,
Michael Schröder,
Wolfgang Rosenstiel:
Towards the restoration of hand grasp function of quadriplegic patients based on an artificial neural net controller using peripheral nerve stimulation - an approach.
ESANN 2003: 427-438 |
| 95 | EE | Martin Stark,
Jan-Hendrik Oetjens,
Wolfgang Rosenstiel:
A Seamless Simulink Based System Desing Flow for Automotive Applications.
FDL 2003: 197-204 |
| 94 | EE | Jürgen Ruf,
Prakash Mohan Peranandam,
Thomas Kropf,
Wolfgang Rosenstiel:
Using Symbolic Simulation for Bounded Property Checking.
FDL 2003: 374-385 |
| 93 | EE | Axel Braun,
Thorsten Schubert,
Martin Stark,
Karsten Haug,
Joachim Gerlach,
Wolfgang Rosenstiel:
Case Study: SystemC-Based Design of an Industrial Exposure Control Unit1.
FDL 2003: 627-636 |
| 92 | EE | Elena P. Sapozhnikova,
Wolfgang Rosenstiel:
AFC: ART-Based Fuzzy Classifier.
KES 2003: 30-36 |
| 91 | | Axel G. Braun,
Jan B. Freuer,
Joachim Gerlach,
Wolfgang Rosenstiel:
Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis.
VLSI-SOC 2003: 55- |
| 2002 |
|---|
| 90 | EE | Axel Siebenborn,
Oliver Bringmann,
Wolfgang Rosenstiel:
Worst-case performance analysis of parallel, communicating software processes.
CODES 2002: 37-42 |
| 89 | EE | Joseph Borel,
G. Matheron,
Ahmed Amine Jerraya,
S. Resve,
M. Rogers,
Wolfgang Rosenstiel,
Irmtraud Rugen-Herzig,
F. Theewen:
MEDEA+ and ITRS Roadmaps.
DATE 2002: 328-329 |
| 88 | EE | Ralf Seepold,
Natividad Martínez Madrid,
Andreas Vörg,
Wolfgang Rosenstiel,
Martin Radetzki,
P. Neumann,
J. Haase:
A Qualification Platform for Design Reuse.
ISQED 2002: 75-80 |
| 87 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Carsten Menn:
Controller Estimation for FPGA Target Architectures during High-Level Synthesis.
ISSS 2002: 56-61 |
| 86 | EE | Frank Hoehn,
Ekkehard Lindner,
Hermann A. Mayer,
Thomas Hermle,
Wolfgang Rosenstiel:
Neural Networks Evaluating NMR Data: An Approach To Visualize Similarities and Relationships of Sol-Gel Derived Inorganic-Organic and Organometallic Hybrid Polymers1.
Journal of Chemical Information and Computer Sciences 42(1): 36-45 (2002) |
| 2001 |
|---|
| 85 | EE | Tommy Kuhn,
Tobias Oppold,
Markus Winterholer,
Wolfgang Rosenstiel,
Mark Edwards,
Yaron Kashai:
A Framework for Object Oriented Hardware Specification, Verification, and Synthesis.
DAC 2001: 413-418 |
| 84 | EE | Daniel Gajski,
Eugenio Villar,
Wolfgang Rosenstiel,
Vassilios Gerousis,
D. Barton,
J. Plantin,
S. E. Ericsson,
Patrizia Cavalloro,
Gjalt G. de Jong:
C/C++: progress or deadlock in system-level specification.
DATE 2001: 136-137 |
| 83 | EE | Jürgen Ruf,
Dirk W. Hoffmann,
Joachim Gerlach,
Thomas Kropf,
Wolfgang Rosenstiel,
Wolfgang Müller:
The simulation semantics of systemC.
DATE 2001: 64-70 |
| 82 | EE | Jürgen Ruf,
Dirk W. Hoffmann,
Thomas Kropf,
Wolfgang Rosenstiel:
Simulation-guided property checking based on a multi-valued AR-automata.
DATE 2001: 742-748 |
| 81 | EE | Martin Bogdan,
Wolfgang Rosenstiel:
Detection of cluster in Self-Organizing Maps for controlling a prostheses using nerve signals.
ESANN 2001: 131-136 |
| 80 | | Tommy Kuhn,
Tobias Oppold,
C. Schulz-Key,
Markus Winterholer,
Wolfgang Rosenstiel,
Mark Edwards,
Yaron Kashai:
Object oriented hardware synthesis and verification.
ISSS 2001: 189-194 |
| 79 | | Wolfgang Rosenstiel,
Brian Bailey,
Masahiro Fujita,
Guang R. Gao,
Rajesh K. Gupta,
Preeti Ranjan Panda:
New design paradigms.
ISSS 2001: 94 |
| 2000 |
|---|
| 78 | EE | Tommy Kuhn,
Wolfgang Rosenstiel:
Java based object oriented hardware specification and synthesis.
ASP-DAC 2000: 579-582 |
| 77 | EE | Masaharu Imai,
Gary Smith,
Steven Schulz,
Karen Bartleson,
Daniel Gajski,
Wolfgang Rosenstiel,
Peter Flake,
Hiroto Yasuura:
One language or more?: how can we design an SoC at a system level?
ASP-DAC 2000: 653-654 |
| 76 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Carsten Menn:
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation.
DATE 2000: 326-332 |
| 75 | EE | Joseph Borel,
Frank Ghenassia,
Jean-Jacques Bronner,
Irmtraud Rugen-Herzig,
Wolfgang Rosenstiel,
Anton Sauer:
A Design Automation Roadmap for Europe Panel discussion.
DATE 2000: 510- |
| 74 | EE | André Hergenhan,
Wolfgang Rosenstiel:
Static Timing Analysis of Embedded Software on Advanced Processor Architectures.
DATE 2000: 552-559 |
| 73 | EE | Gunter Haug,
Udo Kebschull,
Wolfgang Rosenstiel:
A Hardware Platform for VLIW Based Emulation of Digital Designs.
DATE 2000: 747 |
| 72 | | Udo Heuser,
Wolfgang Rosenstiel:
Automatic Generation of Local Internet Catalogues Using the Hierarchical Radius-based Competitive Learning.
ECAI 2000: 306-310 |
| 71 | EE | Dirk W. Hoffmann,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Simulation Meets Verification: Checking Temporal Properties in SystemC.
EUROMICRO 2000: 1435- |
| 70 | EE | Tobias Grundmann,
Marcus Ritt,
Wolfgang Rosenstiel:
Object-Oriented Message-Passing with TPO++ (Research Note).
Euro-Par 2000: 1081-1084 |
| 69 | EE | Karlheinz Weiß,
Carsten Oetker,
Igor Katchan,
Thorsten Steckstor,
Wolfgang Rosenstiel:
Power estimation approach for SRAM-based FPGAs.
FPGA 2000: 195-202 |
| 68 | EE | Joachim Gerlach,
Wolfgang Rosenstiel:
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration.
ICCD 2000: 545-548 |
| 67 | EE | Tobias Grundmann,
Marcus Ritt,
Wolfgang Rosenstiel:
TPO++: An Object-Oriented Message-Passing Library in C++.
ICPP 2000: 43-50 |
| 66 | EE | Carsten Nitsch,
Karlheinz Weiß,
Thorsten Steckstor,
Wolfgang Rosenstiel:
Embedded System Architecture Design Based on Real-Time Emulation.
IEEE International Workshop on Rapid System Prototyping 2000: 228-233 |
| 65 | EE | Wolfgang Rosenstiel:
Embedded Java.
ISSS 2000: 172 |
| 64 | EE | L. Ludwig,
Elena P. Sapozhnikova,
V. P. Lunin,
Wolfgang Rosenstiel:
Error Classification and Yield Prediction of Chips in Semiconductor Industry Applications.
Neural Computing and Applications 9(3): 202-210 (2000) |
| 1999 |
|---|
| 63 | EE | Cordula Hansen,
Francisco Nascimento,
Wolfgang Rosenstiel:
An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications.
DAC 1999: 678-683 |
| 62 | EE | Tommy Kuhn,
Wolfgang Rosenstiel,
Udo Kebschull:
Description and Simulation of Hardware/Software Systems with Java.
DAC 1999: 790-793 |
| 61 | EE | Annette Reutter,
Wolfgang Rosenstiel:
An Efficient Reuse System for Digital Circuit Design.
DATE 1999: 38-43 |
| 60 | EE | Cristina Barna,
Wolfgang Rosenstiel:
Object-Oriented Reuse Methodology for VHDL.
DATE 1999: 689- |
| 59 | EE | Karlheinz Weiß,
Thorsten Steckstor,
Wolfgang Rosenstiel:
Emulation of a Fast Reactive Embedded System using a Real Time Operating System.
DATE 1999: 764-765 |
| 58 | EE | Walter Lange,
Wolfgang Rosenstiel:
VHDL Description and High-Level Synthesis of an ATM Layer Circuit.
EUROMICRO 1999: 1519- |
| 57 | EE | Karlheinz Weiß,
Thorsten Steckstor,
Gernot Koch,
Wolfgang Rosenstiel:
Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System.
FPGA 1999: 235-242 |
| 56 | | Oliver Bringmann,
Wolfgang Rosenstiel:
Hierarchische Synthese für die Emulation von integrierten Steuerungssystemen.
GI Jahrestagung 1999: 146-153 |
| 55 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Annette Muth,
Georg Färber,
Frank Slomka,
Richard Hofmann:
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping.
IEEE International Workshop on Rapid System Prototyping 1999: 114-119 |
| 54 | EE | Karlheinz Weiß,
Thorsten Steckstor,
Wolfgang Rosenstiel:
Performance Analysis of a RTOS by Emulation of an Embedded System.
IEEE International Workshop on Rapid System Prototyping 1999: 146- |
| 53 | | Stephen Schmitt,
Wolfgang Rosenstiel:
Der Einsatz von Jini für die Realisierung durchgängiger Steuerungskonzepte in verteilten eingebetteten Systemen.
Java-Informations-Tage 1999: 223-232 |
| 52 | EE | Elena P. Sapozhnikova,
V. P. Lunin,
L. Ludwig,
Wolfgang Rosenstiel:
The use of dARTMAP and fuzzy ARTMAP to solve the quality testing task in semiconductor industry.
KES 1999: 361-364 |
| 51 | EE | Martin Bogdan,
Wolfgang Rosenstiel:
Application of Artificial Neural Networks for Different Engineering Problems.
SOFSEM 1999: 277-294 |
| 50 | EE | Rolf Hilgendorf,
Gerald J. Heim,
Wolfgang Rosenstiel:
Evaluation of branch-prediction methods on traces from commercial applications.
IBM Journal of Research and Development 43(4): 579-594 (1999) |
| 1998 |
|---|
| 49 | | Ch. Trautwein,
Wolfgang Rosenstiel:
Elektronik-CAD-Anwendung im WWW.
CAD 1998: 251-261 |
| 48 | EE | Joachim Gerlach,
Wolfgang Rosenstiel:
A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment.
DATE 1998: 226- |
| 47 | EE | Wolfgang Rosenstiel:
Formal Verification: A New Standard CAD Tool for the Industrial Design Flow.
DATE 1998: 422- |
| 46 | EE | Cordula Hansen,
Arno Kunzmann,
Wolfgang Rosenstiel:
Verification by Simulation Comparison using Interface Synthesis.
DATE 1998: 436- |
| 45 | EE | Oliver Bringmann,
Wolfgang Rosenstiel:
Cross-Level Hierarchical High-Level Synthesis.
DATE 1998: 451-456 |
| 44 | EE | Wolfgang Rosenstiel:
Next Generation System Level Design Tools.
DATE 1998: 488- |
| 43 | EE | Hans-Georg Martin,
Wolfgang Rosenstiel:
A Comparing Study of Technology Mapping for FPGA.
DATE 1998: 939-940 |
| 42 | EE | Karlheinz Weiß,
Ronny Kistner,
Arno Kunzmann,
Wolfgang Rosenstiel:
Analysis of the XC6000 Architecture for Embedded System Design.
FCCM 1998: 245- |
| 41 | EE | Gunter Haug,
Wolfgang Rosenstiel:
Reconfigurable Hardware as Shared Resource for Parallel Threads.
FCCM 1998: 320-321 |
| 40 | EE | Karlheinz Weiß,
Ronny Kistner,
Arno Kunzmann,
Wolfgang Rosenstiel:
Advantages of the XC6000 Architecture for Embedded System Design (Abstract).
FPGA 1998: 255 |
| 39 | EE | Gunter Haug,
Wolfgang Rosenstiel:
Reconfigurable Hardware as Shared Resource in Multipurpose Computers.
FPL 1998: 149-158 |
| 38 | EE | Björn Steckelbach,
Till Bubeck,
Ulrich Fößmeier,
Michael Kaufmann,
Marcus Ritt,
Wolfgang Rosenstiel:
Visualization of Parallel Execution Graphs.
Graph Drawing 1998: 403-412 |
| 37 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Dirk Reichardt:
Synchronization Detection for Multi-Process Hierarchical Synthesis.
ISSS 1998: 105-110 |
| 36 | EE | T. Buchholz,
Gunter Haug,
Udo Kebschull,
Gernot Koch,
Wolfgang Rosenstiel:
Behavioral Emulation of Synthesized RT-Level Descriptions Using VLIW Architectures.
International Workshop on Rapid System Prototyping 1998: 70- |
| 35 | | Klaus Beschorner,
Wolfgang Rosenstiel:
Realisierung einer Client/Server-Anwendung mit CORBA und Java unter Berücksichtigung bestehender C++-Komponenten.
Java-Informations-Tage 1998: 224-237 |
| 34 | EE | André Hergenhan,
Christoph Weiler,
Karlheinz Weiß,
Wolfgang Rosenstiel:
Value-Added Services in Industrial Automation.
Services and Visualization: Towards User-Friendly Design 1998: 75-89 |
| 33 | EE | Gernot Koch,
Wolfgang Rosenstiel,
Udo Kebschull:
Breakpoints and breakpoint detection in source-level emulation.
ACM Trans. Design Autom. Electr. Syst. 3(2): 209-230 (1998) |
| 1997 |
|---|
| 32 | | Kurt Antreich,
Franz J. Rammig,
Wolfgang Rosenstiel,
Detlef Schmid,
Klaus Waldschmidt:
DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme.
GI Jahrestagung 1997: 93-101 |
| 31 | EE | Oliver Bringmann,
Wolfgang Rosenstiel:
Resource sharing in hierarchical synthesis.
ICCAD 1997: 318-325 |
| 30 | EE | Gernot Koch,
Udo Kebschull,
Wolfgang Rosenstiel:
Co-Emulation and Debugging of HW/SW-Systems.
ISSS 1997: 120-125 |
| 29 | | Kurt Antreich,
Franz J. Rammig,
Wolfgang Rosenstiel,
Detlef Schmid,
Klaus Waldschmidt:
DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme.
Inform., Forsch. Entwickl. 12(4): 220-223 (1997) |
| 28 | | Josef Göppert,
Wolfgang Rosenstiel:
The Continuous Interpolating Self-organizing Map.
Neural Processing Letters 5(3): 185-192 (1997) |
| 1996 |
|---|
| 27 | EE | Wolfram Hardt,
Wolfgang Rosenstiel:
Speed-up estimation for HW/SW-systems.
CODES 1996: 36-43 |
| 26 | EE | Heinz-Josef Eikerling,
Wolfram Hardt,
Joachim Gerlach,
Wolfgang Rosenstiel:
A Methodology for Rapid Analysis and Optimization of Embedded Systems.
ECBS 1996: 252-259 |
| 25 | EE | E. Schubert,
Wolfgang Rosenstiel:
Combined Spectral Techniques for Boolean Matching.
FPGA 1996: 38-43 |
| 24 | EE | Jörg Wilberg,
A. Kuth,
Raul Camposano,
Wolfgang Rosenstiel,
Heinrich Theodor Vierhaus:
A Design Exploration Environment.
Great Lakes Symposium on VLSI 1996: 77-80 |
| 23 | | Thomas Crämer,
Josef Göppert,
Wolfgang Rosenstiel:
Modeling Psychological Stereotypes in Self-Organizing Maps.
ICANN 1996: 905-910 |
| 22 | EE | Gernot Koch,
Udo Kebschull,
Wolfgang Rosenstiel:
Breakpoints and Breakpoint Detection in Source Level Emulation.
ISSS 1996: 26- |
| 1995 |
|---|
| 21 | EE | Ulrich Weinmann,
Oliver Bringmann,
Wolfgang Rosenstiel:
Device selection for system partitioning.
EURO-DAC 1995: 2-7 |
| 20 | EE | Gernot Koch,
Udo Kebschull,
Wolfgang Rosenstiel:
Debugging of behavioral VHDL specifications by source level emulation.
EURO-DAC 1995: 256-261 |
| 19 | EE | Jürgen Schubert,
Arno Kunzmann,
Wolfgang Rosenstiel:
Reduced design time by load distribution with CAD framework methodology information.
EURO-DAC 1995: 314-319 |
| 18 | | Till Bubeck,
M. Hiller,
Wolfgang Küchlin,
Wolfgang Rosenstiel:
Distributed Symbolic Computation with DTS.
IRREGULAR 1995: 231-248 |
| 17 | | Josef Göppert,
Wolfgang Rosenstiel:
Neurons with Continuous Varying Activation in Self-Organizing Maps.
IWANN 1995: 419-426 |
| 1994 |
|---|
| 16 | EE | Gernot Koch,
Udo Kebschull,
Wolfgang Rosenstiel:
A prototyping environment for hardware/software codesign in the COBRA project.
CODES 1994: 10-16 |
| 15 | EE | Jörg Wilberg,
Raul Camposano,
Wolfgang Rosenstiel:
Design flow for hardware/software cosynthesis of a video compression system.
CODES 1994: 73-80 |
| 14 | EE | Xun Xiong,
Edna Barros,
Wolfgang Rosenstiel:
A method for partitioning UNITY language in hardware and software.
EURO-DAC 1994: 220-225 |
| 13 | EE | P. Gutberlet,
Wolfgang Rosenstiel:
Timing preserving interface transformations for the synthesis of behavioral VHDL.
EURO-DAC 1994: 618-623 |
| 12 | EE | Marc Wendling,
Wolfgang Rosenstiel:
A hardware environment for prototyping and partitioning based on multiple FPGAs.
EURO-DAC 1994: 77-82 |
| 11 | | J. Wedeck,
Wolfgang Rosenstiel:
Compiling C Programs into Threads.
EUROSIM 1994: 153-160 |
| 10 | | Hans-Jürgen Brand,
Dietmar Mueller,
Wolfgang Rosenstiel:
Specification and Synthesis of Complex Arithmetic Operators for FPGAs.
FPL 1994: 78-88 |
| 1992 |
|---|
| 9 | | Peter Marwedel,
Wolfgang Rosenstiel:
Synthese von Register-Transfer-Strukturen aus Verhaltensbeschriebungen.
Informatik Spektrum 15(1): 5-22 (1992) |
| 1990 |
|---|
| 8 | EE | Heinrich Krämer,
Wolfgang Rosenstiel:
System synthesis using behavioural descriptions.
EURO-DAC 1990: 277-282 |
| 7 | | P. Gutberlet,
Heinrich Krämer,
Wolfgang Rosenstiel:
CASCH - ein Scheduling-Algorithmus für "High-Level"-Synthese.
Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme 1990: 143-156 |
| 1989 |
|---|
| 6 | EE | Raul Camposano,
Wolfgang Rosenstiel:
Synthesizing circuits from behavioural descriptions.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 171-180 (1989) |
| 5 | | Thomas Wecker,
Ramayya Kumar,
Wolfgang Rosenstiel,
Heinrich Krämer,
Michael Neher:
CALLAS - ein System zur automatischen Synthese digitaler Schaltungen.
Inform., Forsch. Entwickl. 4(1): 37-54 (1989) |
| 1988 |
|---|
| 4 | | Wolfgang Eppler,
Pablo Castro,
Wolfgang Rosenstiel:
Entwurf einer integrierten Schaltung zur Beschleunigung von Koordinatentransformationen mit einem Silicon Compiler.
GI Jahrestagung (2) 1988: 52-65 |
| 1986 |
|---|
| 3 | EE | Hans-Joachim Wunderlich,
Wolfgang Rosenstiel:
On fault modeling for dynamic MOS circuits.
DAC 1986: 540-546 |
| 1984 |
|---|
| 2 | | Detlef Schmid,
Raul Camposano,
Wolfgang Rosenstiel:
Automatischer Entwurf hochintegrierter Schaltungen aus Beschreibungen der Schaltungsfunktion.
GI Jahrestagung 1984: 391-406 |
| 1981 |
|---|
| 1 | | Wolfgang Rosenstiel:
RNL - A Language for Digital Systems Design Based on Nets.
Selected Papers from the First and the Second European Workshop on Application and Theory of Petri Nets 1981: 50-55 |
