Keishi Sakanushi

2007
16	EE	Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. ASP-DAC 2007: 286-291
15	EE	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: A low power VLIW processor generation method by means of extracting non-redundant activation conditions. CODES+ISSS 2007: 227-232
14	EE	M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC CoRR abs/0710.4746: (2007)
13	EE	Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto: Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. IEICE Transactions 90-A(12): 2800-2809 (2007)
2006
12	EE	Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa: Pack instruction generation for media pUsing multi-valued decision diagram. CODES+ISSS 2006: 154-159
11	EE	Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. VLSI-SoC 2006: 290-295
2005
10	EE	M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Enabling RTOS simulation modeling in a system level design language. ASP-DAC 2005: 936-939
9	EE	M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. DATE 2005: 554-559
2004
8	EE	Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Synthesizable HDL generation method for configurable VLIW processors. ASP-DAC 2004: 842-845
7	EE	Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Architecture-Level Performance Estimation for IP-Based Embedded Systems. DATE 2004: 1002-1007
6	EE	H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. ICDCS Workshops 2004: 824-830
5		Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai: S-sequence: a new floorplan representation method preserving room abutment relationships. ISCAS (4) 2004: 505-508
2003
4	EE	Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai: A Code Selection Method for SIMD Processors with PACK Instructions. SCOPES 2003: 66-80
2002
3	EE	Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin: An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. DATE 2002: 61-68
1998
2	EE	Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani: The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. ICCAD 1998: 267-274
1	EE	Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita: The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ICCAD 1998: 418-425

Coauthor Index

1	H. M. AbdElSalam	[6]
2	Masaaki Abe	[16]
3	M. Abdelsalam Hassan	[9] [10] [14]
4	Masaharu Imai	[4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
5	Yohei Ishimaru	[5]
6	Hirofumi Iwato	[15]
7	Liyan Jin	[3]
8	Yoji Kajitani	[1] [2] [3]
9	Masahiro Kawakita	[1]
10	Shinsuke Kobayashi	[4] [5] [6] [8]
11	Yuki Kobayashi	[8]
12	Nobu Matsumoto	[12] [13]
13	Masaki Nakagawa	[12]
14	Shigetoshi Nakatake	[1] [2]
15	Koji Okuda	[8]
16	Yutaka Ota	[12] [13]
17	Takeshi Shiro	[16]
18	Hiroki Tagawa	[13]
19	Yoshinori Takeuchi	[4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
20	Hiroaki Tanaka	[4] [12] [13]
21	Ittetsu Taniguchi	[11]
22	Kyoko Ueda	[7] [11]
23	Changwen Zhuang	[3]

Colors in the list of coauthors