| 2009 |
|---|
| 37 | EE | Xiangrong Zhou,
Chenjie Yu,
Peter Petrov:
Temperature-aware register reallocation for register file power-density minimization.
ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
| 36 | EE | Xiangrong Zhou,
Peter Petrov:
Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systems.
ACM Trans. Embedded Comput. Syst. 8(2): (2009) |
| 2008 |
|---|
| 35 | EE | Chenjie Yu,
Peter Petrov:
Distributed and low-power synchronization architecture for embedded multiprocessors.
CODES+ISSS 2008: 73-78 |
| 34 | EE | Xiangrong Zhou,
Chenjie Yu,
Peter Petrov:
Compiler-driven register re-assignment for register file power-density and temperature reduction.
DAC 2008: 750-753 |
| 33 | EE | Chenjie Yu,
Peter Petrov:
Latency and bandwidth efficient communication through system customization for embedded multiprocessors.
DAC 2008: 766-771 |
| 32 | EE | Xiangrong Zhou,
Chenjie Yu,
Alokika Dash,
Peter Petrov:
Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 31 | EE | Xiangrong Zhou,
Peter Petrov:
Heterogeneously tagged caches for low-power embedded systems with virtual memory support.
ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
| 30 | EE | Xiangrong Zhou,
Peter Petrov:
Direct address translation for virtual memory in energy-efficient embedded systems.
ACM Trans. Embedded Comput. Syst. 8(1): (2008) |
| 2007 |
|---|
| 29 | EE | Rakesh Reddy,
Peter Petrov:
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems.
CASES 2007: 198-207 |
| 28 | EE | Chenjie Yu,
Peter Petrov:
Aggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processors.
CODES+ISSS 2007: 245-250 |
| 27 | EE | Xiangrong Zhou,
Peter Petrov:
The interval page table: virtual memory support in real-time and memory-constrained embedded systems.
SBCCI 2007: 294-299 |
| 26 | EE | Peter Petrov,
Alex Orailoglu:
Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory.
International Journal of Parallel Programming 35(2): 157-177 (2007) |
| 2006 |
|---|
| 25 | EE | Xiangrong Zhou,
Peter Petrov:
Low-power cache organization through selective tag translation for embedded processors with virtual memory support.
ACM Great Lakes Symposium on VLSI 2006: 398-403 |
| 24 | EE | Xiangrong Zhou,
Peter Petrov:
Rapid and low-cost context-switch through embedded processor customization for real-time and control applications.
DAC 2006: 352-357 |
| 23 | EE | Alokika Dash,
Peter Petrov:
Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering.
DSD 2006: 79-82 |
| 2005 |
|---|
| 22 | EE | Xiangrong Zhou,
Peter Petrov:
Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors.
CODES+ISSS 2005: 33-38 |
| 21 | EE | Peter Petrov,
Daniel Tracy,
Alex Orailoglu:
Energy-effcient physically tagged caches for embedded processors with virtual memory.
DAC 2005: 17-22 |
| 20 | EE | Xiangrong Zhou,
Peter Petrov:
Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems.
SBCCI 2005: 86-91 |
| 19 | EE | Peter Petrov,
Alex Orailoglu:
A reprogrammable customization framework for efficient branch resolution in embedded processors.
ACM Trans. Embedded Comput. Syst. 4(2): 452-468 (2005) |
| 2004 |
|---|
| 18 | EE | Peter Petrov,
Alex Orailoglu:
Transforming Binary Code for Low-Power Embedded Processors.
IEEE Micro 24(3): 21-33 (2004) |
| 17 | EE | Peter Petrov,
Alex Orailoglu:
Low-power instruction bus encoding for embedded processors.
IEEE Trans. VLSI Syst. 12(8): 812-826 (2004) |
| 16 | EE | Peter Petrov,
Alex Orailoglu:
Tag compression for low power in dynamically customizable embedded processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1031-1047 (2004) |
| 2003 |
|---|
| 15 | EE | Peter Petrov,
Alex Orailoglu:
Power Efficiency through Application-Specific Instruction Memory Transformations.
DATE 2003: 10030-10035 |
| 14 | EE | Peter Petrov,
Alex Orailoglu:
Low-power Branch Target Buffer for Application-Specific Embedded Processors.
DSD 2003: 158-165 |
| 13 | EE | Peter Petrov,
Alex Orailoglu:
Customizable Embedded Processor Architectures.
DSD 2003: 468-475 |
| 12 | EE | Peter Petrov,
Alex Orailoglu:
Compiler-Based Register Name Adjustment for Low-Power Embedded Processors.
ICCAD 2003: 523-528 |
| 11 | EE | Peter Petrov,
Alex Orailoglu:
Virtual Page Tag Reduction for Low-power TLBs.
ICCD 2003: 371-374 |
| 10 | EE | Peter Petrov,
Alex Orailoglu:
Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors.
IEEE Design & Test of Computers 20(1): 18-25 (2003) |
| 2002 |
|---|
| 9 | EE | Peter Petrov,
Alex Orailoglu:
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors.
CODES 2002: 181-186 |
| 8 | EE | Peter Petrov,
Alex Orailoglu:
Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches.
DATE 2002: 1065-1071 |
| 7 | EE | Alex Orailoglu,
Peter Petrov:
Low-Power Data Memory Communication for Application-Specific Embedded Processors.
ISSS 2002: 219-224 |
| 2001 |
|---|
| 6 | EE | Sobeeh Almukhaizim,
Peter Petrov,
Alex Orailoglu:
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit.
Asian Test Symposium 2001: 319-324 |
| 5 | EE | Peter Petrov,
Alex Orailoglu:
Towards effective embedded processors in codesigns: customizable partitioned caches.
CODES 2001: 79-84 |
| 4 | EE | Peter Petrov,
Alex Orailoglu:
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors.
DAC 2001: 512-517 |
| 3 | | Peter Petrov,
Alex Orailoglu:
Data cache energy minimizations through programmable tag size matching to the applications.
ISSS 2001: 113-117 |
| 2 | EE | Peter Petrov,
Alex Orailoglu:
Performance and power effectiveness in embedded processors customizable partitioned caches.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1309-1318 (2001) |
| 1991 |
|---|
| 1 | EE | Boyan Dimitrov,
Zohel Khalil,
Nikolay Kolev,
Peter Petrov:
On the Optimal Total Processing Time Using Checkpoints.
IEEE Trans. Software Eng. 17(5): 436-442 (1991) |
