| 2005 |
|---|
| 15 | EE | Michael W. Beattie,
Hui Zheng,
Anirudh Devgan,
Byron Krauter:
Spatially distributed 3D circuit models.
DAC 2005: 153-158 |
| 2004 |
|---|
| 14 | EE | Michael W. Beattie,
Lawrence T. Pileggi:
Parasitics extraction with multipole refinement.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 288-292 (2004) |
| 2002 |
|---|
| 13 | EE | Tao Lin,
Michael W. Beattie,
Lawrence T. Pileggi:
On the efficacy of simplified 2D on-chip inductance models.
DAC 2002: 757-762 |
| 12 | EE | Tao Lin,
Michael W. Beattie,
Lawrence T. Pileggi:
On-Chip Inductance Models: 3D or Not 3D?
DATE 2002: 1112 |
| 11 | EE | Hui Zheng,
Lawrence T. Pileggi,
Michael W. Beattie,
Byron Krauter:
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses.
DATE 2002: 628-633 |
| 10 | EE | Michael W. Beattie,
Lawrence T. Pileggi:
On-chip induction modeling: basics and advanced methods.
IEEE Trans. VLSI Syst. 10(6): 712-729 (2002) |
| 2001 |
|---|
| 9 | EE | Michael W. Beattie,
Lawrence T. Pileggi:
Inductance 101: Modeling and Extraction.
DAC 2001: 323-328 |
| 8 | EE | Michael W. Beattie,
Lawrence T. Pileggi:
Modeling Magnetic Coupling for On-Chip Interconnect.
DAC 2001: 335-340 |
| 7 | EE | Michael W. Beattie,
Lawrence T. Pileggi:
Efficient inductance extraction via windowing.
DATE 2001: 430-436 |
| 6 | EE | Michael W. Beattie,
Byron Krauter,
Lale Alatan,
Lawrence T. Pileggi:
Equipotential shells for efficient inductance extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 70-79 (2001) |
| 2000 |
|---|
| 5 | | Michael W. Beattie,
Satrajit Gupta,
Lawrence T. Pileggi:
Hierarchical Interconnect Circuit Models.
ICCAD 2000: 215-221 |
| 1999 |
|---|
| 4 | EE | Michael W. Beattie,
Lawrence T. Pileggi:
IC Analyses Including Extracted Inductance Models.
DAC 1999: 915-920 |
| 3 | EE | Michael W. Beattie,
Lawrence T. Pileggi:
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement.
ICCAD 1999: 437-444 |
| 2 | EE | Michael W. Beattie,
Lawrence T. Pileggi:
Error bounds for capacitance extraction via window techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 311-321 (1999) |
| 1997 |
|---|
| 1 | EE | Michael W. Beattie,
Lawrence T. Pileggi:
Bounds for BEM Capacitance Extraction.
DAC 1997: 133-136 |
