Erich Barke

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53EEPhilipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl: Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22
52EEMarkus Olbrich, Erich Barke: Distribution arithmetic for stochastical analysis. ASP-DAC 2008: 537-542
51EEDarius Grabowski, Markus Olbrich, Erich Barke: Analog circuit simulation using range arithmetics. ASP-DAC 2008: 762-767
50EEPeter Leppelt, Erich Barke: Determining the Technical Complexity of Integrated Circuits. DATE 2008: 935
49EEThomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke: A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. DDECS 2008: 54-58
48EES. Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt: Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). FDL 2008: 73-77
47EEPhilipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl: Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI 2007: 43-48
46EEHedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke: Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. DAC 2007: 706-711
45EEM. Zhang, Markus Olbrich, D. Seider, M. Frerichs, H. Kinzelbach, Erich Barke: CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. DATE 2007: 243-248
44 Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke: Range Arithmetics to Speed up Reachability Analysis of Analog Systems. FDL 2007: 38-43
43EEJan Torben Weinkopf, Klaus Harbich, Erich Barke: Incremental Fault Emulation. FPL 2007: 542-545
42EEMatthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten: Algorithms for automatic length compensation of busses in analog integrated circuits. ISPD 2007: 159-166
41EEDaniel Platte, S. Jing, R. Sommer, Erich Barke: Using Sequential Equations to Improve Efficiency and Robustness. FDL 2006: 83-90
40EEJan Torben Weinkopf, Klaus Harbich, Erich Barke: Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. FPL 2006: 1-6
39EEDarius Grabowski, Christoph Grimm, Erich Barke: Semi-symbolic modeling and simulation of circuits and systems. ISCAS 2006
38EEDarius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke: Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. Electr. Notes Theor. Comput. Sci. 153(3): 37-52 (2006)
37EELars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten: Routing of analog busses with parasitic symmetry. ISPD 2005: 14-19
36EEMarkus Olbrich, Erich Barke: Placement Using a Localization Probability Model (LPM). DATE 2004: 1412
35EELutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. DATE 2004: 442-447
34EEIdris Kaya, Silke Salewski, Markus Olbrich, Erich Barke: Wirelength Reduction Using 3-D Physical Design. PATMOS 2004: 453-462
33 Andreas Hermann, Markus Olbrich, Erich Barke: Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. VLSI-SOC 2003: 13-18
32EEWalter Hartong, Lars Hedrich, Erich Barke: On Discrete Modeling and Model Checking for Nonlinear Analog Systems. CAV 2002: 401-413
31EEWalter Hartong, Lars Hedrich, Erich Barke: Model checking algorithms for analog verification. DAC 2002: 542-547
30EEWalter Hartong, Lars Hedrich, Erich Barke: An Approach to Model Checking for Nonlinear Analog Systems. DATE 2002: 1080
29EEJoerg Abke, Erich Barke: A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . DATE 2002: 1085
28EERolf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke: Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. DATE 2002: 274-278
27EEAndreas C. Lemke, Lars Hedrich, Erich Barke: Analog circuit sizing based on formal methods using affine arithmetic. ICCAD 2002: 486-489
26EESilke Salewski, Erich Barke: An Upper Bound for 3D Slicing Floorplans. VLSI Design 2002: 567-572
25EEJoachim Küter, Erich Barke: Architecture driven partitioning. DATE 2001: 479-487
24EEMarkus Olbrich, Achim Rein, Erich Barke: An improved hierarchical classification algorithm for structural analysis of integrated circuits. DATE 2001: 807
23EEKlaus Harbich, Erich Barke: PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. FPL 2001: 133-141
22EEJoerg Abke, Erich Barke: A New Placement Method for Direct Mapping into LUT-Based FPGAs. FPL 2001: 27-36
21EEMark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch: CHIPDESIGN - A Novel Project-oriented Microelectronics Course. MSE 2001: 71-72
20 Dimitrios Soudris, Peter Pirsch, Erich Barke: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings Springer 2000
19EEThorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke: A current driven routing and verification methodology for analog applications. DAC 2000: 385-389
18EEThorsten Adler, Erich Barke: Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. DATE 2000: 446-450
17EEMatthias Ringe, Thomas Lindenkreuz, Erich Barke: Static Timing Analysis Taking Crosstalk into Account. DATE 2000: 451-
16EEJoerg Abke, Erich Barke: CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. FPL 2000: 191-200
15EEAndreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel: PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. PATMOS 2000: 306-315
14EEKlaus Harbich, Jörn Stohmann, Erich Barke, Ludwig Schwoerer: A Case Study: Logic Emulation - Pitfalls and Solutions. IEEE International Workshop on Rapid System Prototyping 1999: 160-
13EEJoerg Abke, Erich Barke, Jörn Stohmann: A Universal Module Generator for LUT-Based FPGAs. IEEE International Workshop on Rapid System Prototyping 1999: 230-235
12 Reza Sedaghat-Maman, Erich Barke: Real Time Fault Injection Using Logic Emulators. ASP-DAC 1998: 475-479
11EELars Hedrich, Erich Barke: A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. DATE 1998: 649-
10EEMatthias Ringe, Thomas Lindenkreuz, Erich Barke: Path Verification Using Boolean Satisfiability. DATE 1998: 965-966
9EEJörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke: An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. FPL 1998: 79-88
8 Jörn Stohmann, Erich Barke: A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. ICCD 1997: 489-495
7EECarsten Borchers, Lars Hedrich, Erich Barke: Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. DAC 1996: 236-239
6 Jörn Stohmann, Erich Barke: A Universal CLA Adder Generator for SRAM-Based FPGAs. FPL 1996: 44-54
5EEDirk Behrens, Klaus Harbich, Erich Barke: Hierarchical partitioning. ICCAD 1996: 470-477
4EELars Hedrich, Erich Barke: A formal approach to nonlinear analog circuit verification. ICCAD 1995: 123-127
3EEErich Barke: Line-to-ground capacitance calculation for VLSI: a comparison. IEEE Trans. on CAD of Integrated Circuits and Systems 7(2): 295-298 (1988)
2EEErich Barke: Resistance calculation from mask artwork data by finite element method. DAC 1985: 305-311
1 Erich Barke: FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung. Angewandte Informatik 27(8): 328-333 (1985)

Coauthor Index

1Joerg Abke [13] [16] [22] [29]
2Thorsten Adler [18] [19]
3Dirk Behrens [5]
4Volker Meyer zu Bexten [37] [42]
5Carsten Borchers [7]
6Hiltrud Brocke [19]
7Markus Bühler [53]
8Volodymyr Burkhay [35]
9M. Frerichs [45]
10Darius Grabowski [38] [39] [44] [51]
11Christoph Grimm [39] [44]
12Klaus Harbich [5] [9] [14] [23] [40] [43]
13Hedi Harizi [46]
14Walter Hartong [30] [31] [32]
15Robert HauBler [46]
16Lars Hedrich [4] [7] [11] [19] [27] [28] [30] [31] [32] [35] [38]
17Andreas Hermann [33]
18Andreas Herrmann [15]
19S. Hoelldampf [48]
20Thomas Jambor [49]
21S. Jing [41]
22Idris Kaya [34]
23H. Kinzelbach [45]
24Jürgen Koehl [47] [53]
25Mark Bernd Kulaczewski [21]
26Joachim Küter [25]
27Andreas C. Lemke [27]
28Peter Leppelt [50]
29Thomas Lindenkreuz [10] [17]
30Lutz Näthke [35]
31Ingmar Neumann [48]
32Joerg Oehmen [28]
33Markus Olbrich [9] [24] [33] [34] [36] [37] [44] [45] [46] [47] [48] [49] [51] [52] [53]
34Philipp V. Panitz [47] [53]
35Peter Pirsch [20] [21]
36Daniel Platte [38] [41]
37Rolf Popp [28]
38Achim Rein [24]
39Matthias Ringe [10] [17]
40Silke Salewski [26] [34]
41Jürgen Schlöffel [15]
42Sebastian Schmidt [48]
43Lars A. Schreiner [37] [42]
44Ludwig Schwoerer [14]
45Reza Sedaghat-Maman [12]
46D. Seider [45]
47Mathias Silvant [15]
48Matthew A. Smith [42]
49R. Sommer [41]
50Dimitrios Soudris (D. J. Soudris) [20]
51Jörn Stohmann [6] [8] [9] [13] [14]
52Jan Torben Weinkopf [40] [43]
53Daniel Zaum [48] [49]
54M. Zhang [45]
55Stefan Zimmerman [21]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)