| 2003 |
|---|
| 6 | EE | Li-Da Huang,
Minghorng Lai,
Martin D. F. Wong,
Youxin Gao:
Maze routing with buffer insertion under transition time constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 91-95 (2003) |
| 2002 |
|---|
| 5 | EE | Li-Da Huang,
Minghorng Lai,
D. F. Wong,
Youxin Gao:
Maze Routing with Buffer Insertion under Transition Time Constraints.
DATE 2002: 702-707 |
| 4 | EE | Minghorng Lai,
Martin D. F. Wong:
Maze routing with buffer insertion and wiresizing.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1205-1209 (2002) |
| 2001 |
|---|
| 3 | EE | Minghorng Lai,
D. F. Wong:
Memory-efficient interconnect optimization.
ASP-DAC 2001: 198-202 |
| 2 | EE | Minghorng Lai,
D. F. Wong:
Slicing tree is a complete floorplan representation.
DATE 2001: 228-232 |
| 2000 |
|---|
| 1 | EE | Minghorng Lai,
D. F. Wong:
Maze routing with buffer insertion and wiresizing.
DAC 2000: 374-378 |
