| 2004 |
|---|
| 79 | EE | Murat R. Becer,
David Blaauw,
Ilan Algor,
Rajendran Panda,
Chanhee Oh,
Vladimir Zolotov,
Ibrahim N. Hajj:
Postroute gate sizing for crosstalk noise reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1670-1677 (2004) |
| 2003 |
|---|
| 78 | EE | Murat R. Becer,
David Blaauw,
Ilan Algor,
Rajendran Panda,
Chanhee Oh,
Vladimir Zolotov,
Ibrahim N. Hajj:
Post-route gate sizing for crosstalk noise reduction.
DAC 2003: 954-957 |
| 77 | EE | Murat R. Becer,
David Blaauw,
Ilan Algor,
Rajendran Panda,
Chanhee Oh,
Vladimir Zolotov,
Ibrahim N. Hajj:
Post-Route Gate Sizing for Crosstalk Noise Reduction.
ISQED 2003: 171-176 |
| 76 | EE | Murat R. Becer,
David T. Blaauw,
Rajendran Panda,
Ibrahim N. Hajj:
Early probabilistic noise estimation for capacitively coupled interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 337-345 (2003) |
| 2002 |
|---|
| 75 | EE | Murat R. Becer,
Vladimir Zolotov,
David Blaauw,
Rajendran Panda,
Ibrahim N. Hajj:
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .
DATE 2002: 456-464 |
| 74 | EE | Geng Bai,
Ibrahim N. Hajj:
Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network.
ISQED 2002: 163-168 |
| 73 | EE | Murat R. Becer,
Rajendran Panda,
David Blaauw,
Ibrahim N. Hajj:
Pre-route Noise Estimation in Deep Submicron Integrated Circuits.
ISQED 2002: 413-418 |
| 72 | EE | Murat R. Becer,
David Blaauw,
Ibrahim N. Hajj,
Rajendran Panda:
Early probabilistic noise estimation for capacitively coupled interconnects.
SLIP 2002: 77-83 |
| 71 | EE | Vikram Saxena,
Farid N. Najm,
Ibrahim N. Hajj:
Estimation of state line statistics in sequential circuits.
ACM Trans. Design Autom. Electr. Syst. 7(3): 455-473 (2002) |
| 70 | EE | Sumant Ramprasad,
Ibrahim N. Hajj,
Farid N. Najm:
A technique for Improving dual-output domino logic.
IEEE Trans. VLSI Syst. 10(4): 508-511 (2002) |
| 2001 |
|---|
| 69 | EE | Geng Bai,
Sudhakar Bobba,
Ibrahim N. Hajj:
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits.
DAC 2001: 295-300 |
| 68 | EE | Sudhakar Bobba,
Ibrahim N. Hajj:
Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits.
ISCAS (5) 2001: 195-198 |
| 67 | EE | Sudhakar Bobba,
Ibrahim N. Hajj:
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models.
ISLPED 2001: 376-381 |
| 66 | EE | Ninglong Lu,
Ibrahim N. Hajj:
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model.
ISQED 2001: 133-138 |
| 65 | EE | Murat R. Becer,
David Blaauw,
Supamas Sirichotiyakul,
Chanhee Oh,
Vladimir Zolotov,
Jingyan Zuo,
Rafi Levy,
Ibrahim N. Hajj:
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.
ISQED 2001: 158- |
| 64 | EE | Geng Bai,
Sudhakar Bobba,
Ibrahim N. Hajj:
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
ISQED 2001: 205-210 |
| 63 | EE | Geng Bai,
Sudhakar Bobba,
Ibrahim N. Hajj:
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
ISQED 2001: 257- |
| 2000 |
|---|
| 62 | EE | Sudhakar Bobba,
Ibrahim N. Hajj:
High-performance bidirectional repeaters.
ACM Great Lakes Symposium on VLSI 2000: 53-58 |
| 61 | | Geng Bai,
Sudhakar Bobba,
Ibrahim N. Hajj:
Simulation and Optimization of the Power Distribution Network in VLSI Circuits.
ICCAD 2000: 481-486 |
| 60 | EE | Sudhakar Bobba,
Ibrahim N. Hajj:
Current-Mode Threshold Logic Gates.
ICCD 2000: 235-240 |
| 59 | EE | Geng Bai,
Sudhakar Bobba,
Ibrahim N. Hajj:
Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
ISQED 2000: 263-268 |
| 58 | EE | Murat R. Becer,
Ibrahim N. Hajj:
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling.
ISQED 2000: 51-58 |
| 57 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos,
G. Stamoulis:
Architectural and compiler techniques for energy reduction in high-performance microprocessors.
IEEE Trans. VLSI Syst. 8(3): 317-326 (2000) |
| 56 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos:
Using dynamic cache management techniques to reduce energy in general purpose processors.
IEEE Trans. VLSI Syst. 8(6): 693-708 (2000) |
| 1999 |
|---|
| 55 | EE | Ninglong Lu,
Ibrahim N. Hajj:
An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications.
Great Lakes Symposium on VLSI 1999: 68- |
| 54 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos,
George D. Stamoulis:
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache.
ICCD 1999: 378-383 |
| 53 | EE | Andreas G. Veneris,
Ibrahim N. Hajj:
Correcting multiple design errors in digital VLSI circuits.
ISCAS (1) 1999: 31-34 |
| 52 | EE | Sumant Ramprasad,
Naresh R. Shanbhag,
Ibrahim N. Hajj:
Low-power distributed arithmetic architectures using nonuniform memory partitioning.
ISCAS (3) 1999: 470-473 |
| 51 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos:
An analytical, transistor-level energy model for SRAM-based caches.
ISCAS (6) 1999: 198-201 |
| 50 | EE | Ninglong Lu,
Ibrahim N. Hajj:
A reduced-order scheme for coupled lumped-distributed interconnect simulation.
ISCAS (6) 1999: 250-253 |
| 49 | EE | Sumant Ramprasad,
Ibrahim N. Hajj,
Farid N. Najm:
An optimization technique for dual-output domino logic.
ISLPED 1999: 258-260 |
| 48 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos:
Using dynamic cache management techniques to reduce energy in a high-performance processor.
ISLPED 1999: 64-69 |
| 47 | EE | Sudhakar Bobba,
Ibrahim N. Hajj,
Naresh R. Shanbhag:
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.
VLSI Design 1999: 358- |
| 46 | EE | Andreas G. Veneris,
Ibrahim N. Hajj,
Srikanth Venkataraman,
W. Kent Fuchs:
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits.
VTS 1999: 58-63 |
| 45 | EE | Sumant Ramprasad,
Naresh R. Shanbhag,
Ibrahim N. Hajj:
A coding framework for low-power address and data busses.
IEEE Trans. VLSI Syst. 7(2): 212-221 (1999) |
| 44 | EE | Sumant Ramprasad,
Naresh R. Shanbhag,
Ibrahim N. Hajj:
Information-theoretic bounds on average signal transition activity [VLSI systems].
IEEE Trans. VLSI Syst. 7(3): 359-368 (1999) |
| 43 | EE | Andreas G. Veneris,
Ibrahim N. Hajj:
Design error diagnosis and correction via test vector simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1803-1816 (1999) |
| 1998 |
|---|
| 42 | EE | Sudhakar Bobba,
Ibrahim N. Hajj:
Maximum Current Estimation in Programmable Logic Arrays.
Great Lakes Symposium on VLSI 1998: 301-306 |
| 41 | EE | Sumant Ramprasad,
Naresh R. Shanbhag,
Ibrahim N. Hajj:
Decorrelating (DECOR) transformations for low-power adaptive filters.
ISLPED 1998: 250-255 |
| 40 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
George D. Stamoulis,
Nikolaos Bellas,
Constantine D. Polychronopoulos:
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.
ISLPED 1998: 70-75 |
| 39 | EE | Sudhakar Bobba,
Ibrahim N. Hajj:
Estimation of maximum current envelope for power bus analysis and design.
ISPD 1998: 141-146 |
| 38 | | Sumant Ramprasad,
Naresh R. Shanbhag,
Ibrahim N. Hajj:
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications.
VLSI Design 1998: 18-23 |
| 1997 |
|---|
| 37 | EE | Sumant Ramprasad,
Naresh R. Shanbhag,
Ibrahim N. Hajj:
Analytical Estimation of Transition Activity From Word-Level Signal Statistics.
DAC 1997: 582-587 |
| 36 | EE | Vikram Saxena,
Farid N. Najm,
Ibrahim N. Hajj:
Monte-Carlo approach for power estimation in sequential circuits.
ED&TC 1997: 416-420 |
| 35 | EE | Andreas G. Veneris,
Ibrahim N. Hajj:
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits.
Great Lakes Symposium on VLSI 1997: 45-50 |
| 34 | EE | Sumant Ramprasad,
Naresh R. Shanbhag,
Ibrahim N. Hajj:
Achievable bounds on signal transition activity.
ICCAD 1997: 126-129 |
| 33 | EE | Tzuhao Chen,
Ibrahim N. Hajj:
GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment.
ICCAD 1997: 555-561 |
| 32 | EE | Pi-Yu Chung,
Ibrahim N. Hajj:
Diagnosis and correction of multiple logic design errors in digital circuits.
IEEE Trans. VLSI Syst. 5(2): 233-237 (1997) |
| 31 | EE | Sumant Ramprasad,
Naresh R. Shanbhag,
Ibrahim N. Hajj:
Analytical estimation of signal transition activity from word-level statistics.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 718-733 (1997) |
| 1996 |
|---|
| 30 | EE | Terry Lee,
Ibrahim N. Hajj,
Elizabeth M. Rudnick,
Janak H. Patel:
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.
VTS 1996: 456-462 |
| 29 | EE | Ping-Chung Li,
Ibrahim N. Hajj:
Computer-aided redesign of VLSI circuits for hot-carrier reliability.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 453-464 (1996) |
| 1995 |
|---|
| 28 | EE | Farid N. Najm,
Shashank Goel,
Ibrahim N. Hajj:
Power Estimation in Sequential Circuits.
DAC 1995: 635-640 |
| 27 | EE | Weitong Chuang,
Sachin S. Sapatnekar,
Ibrahim N. Hajj:
Timing and area optimization for standard-cell VLSI circuit design.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 308-320 (1995) |
| 26 | EE | Terry Lee,
Weitong Chuang,
Ibrahim N. Hajj,
W. Kent Fuchs:
Circuit-level dictionaries of CMOS bridging faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 596-603 (1995) |
| 25 | EE | Harish Kriplani,
Farid N. Najm,
Ibrahim N. Hajj:
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 998-1012 (1995) |
| 1994 |
|---|
| 24 | EE | Weitong Chuang,
Ibrahim N. Hajj:
Delay and area optimization for compact placement by gate resizing and relocation.
ICCAD 1994: 145-148 |
| 23 | | Harish Kriplani,
Farid N. Najm,
Ibrahim N. Hajj:
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.
ISCAS 1994: 435-438 |
| 22 | EE | Pi-Yu Chung,
Yi-Min Wang,
Ibrahim N. Hajj:
Logic design error diagnosis and correction.
IEEE Trans. VLSI Syst. 2(3): 320-332 (1994) |
| 21 | EE | Ping-Chung Li,
Georgios I. Stamoulis,
Ibrahim N. Hajj:
A probabilistic timing approach to hot-carrier effect estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1223-1234 (1994) |
| 1993 |
|---|
| 20 | EE | Georgios I. Stamoulis,
Ibrahim N. Hajj:
Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects.
DAC 1993: 379-383 |
| 19 | EE | Harish Kriplani,
Farid N. Najm,
Ping Yang,
Ibrahim N. Hajj:
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.
DAC 1993: 384-388 |
| 18 | EE | Pi-Yu Chung,
Yi-Min Wang,
Ibrahim N. Hajj:
Diagnosis and Correction of Logic Design Errors in Digital Circuits.
DAC 1993: 503-508 |
| 17 | EE | Weitong Chuang,
Sachin S. Sapatnekar,
Ibrahim N. Hajj:
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area.
ICCAD 1993: 220-223 |
| 16 | | Ping-Chung Li,
Ibrahim N. Hajj:
Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability.
ICCD 1993: 534-537 |
| 15 | | Weitong Chuang,
Ibrahim N. Hajj:
Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection.
ISCAS 1993: 1503-1506 |
| 14 | | Pi-Yu Chung,
Ibrahim N. Hajj,
Janak H. Patel:
Efficient Variable Ordering Heuristics for Shared ROBDD.
ISCAS 1993: 1690-1693 |
| 13 | EE | Andrew T. Yang,
Yu-Hsu Chang,
Daniel G. Saab,
Ibrahim N. Hajj:
Switch-level timing simulation of bipolar ECL circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 516-530 (1993) |
| 1992 |
|---|
| 12 | EE | Harish Kriplani,
Farid N. Najm,
Ibrahim N. Hajj:
Maximum Current Estimation in CMOS Circuits.
DAC 1992: 2-7 |
| 11 | EE | Ping-Chung Li,
Georgios I. Stamoulis,
Ibrahim N. Hajj:
A probabilistic timing approach to hot-carrier effect estimation.
ICCAD 1992: 210-213 |
| 10 | | Pi-Yu Chung,
Ibrahim N. Hajj:
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits.
ITC 1992: 742-751 |
| 1991 |
|---|
| 9 | | Terry Lee,
Ibrahim N. Hajj:
A Switch-Level Matrix Approach to Transistor-Level Fault Simulation.
ICCAD 1991: 554-557 |
| 8 | EE | Farid N. Najm,
Ibrahim N. Hajj,
Ping Yang:
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1372-1381 (1991) |
| 1990 |
|---|
| 7 | | Ibrahim N. Hajj:
An Algebra for Switch-Level Simulation.
ICCAD 1990: 488-491 |
| 6 | EE | Farid N. Najm,
Richard Burch,
Ping Yang,
Ibrahim N. Hajj:
Probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 439-450 (1990) |
| 5 | EE | Farid N. Najm,
Ibrahim N. Hajj:
The complexity of fault detection in MOS VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 995-1001 (1990) |
| 4 | | Ibrahim N. Hajj,
Stig Skelboe:
A multilevel parallel solver for block tridiagonal and banded linear systems.
Parallel Computing 15(1-3): 21-45 (1990) |
| 1989 |
|---|
| 3 | EE | Min-You Wu,
Ibrahim N. Hajj:
Switching network logic approach to sequential MOS circuit design.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(7): 782-794 (1989) |
| 1988 |
|---|
| 2 | EE | Daniel G. Saab,
Andrew T. Yang,
Ibrahim N. Hajj:
Delay Modeling and Time of Bipolar Digital Circuits.
DAC 1988: 288-293 |
| 1987 |
|---|
| 1 | EE | Ibrahim N. Hajj,
Daniel G. Saab:
Switch-Level Logic Simulation of Digital Bipolar Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 251-258 (1987) |
