| 2005 |
|---|
| 6 | EE | Chih-Pin Su,
Chia-Lung Horng,
Chih-Tsun Huang,
Cheng-Wen Wu:
A configurable AES processor for enhanced security.
ASP-DAC 2005: 361-366 |
| 5 | EE | Chih-Pin Su,
Chen-Hsing Wang,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu:
Design and test of a scalable security processor.
ASP-DAC 2005: 372-375 |
| 2004 |
|---|
| 4 | EE | Mao-Yin Wang,
Chih-Pin Su,
Chih-Tsun Huang,
Cheng-Wen Wu:
An HMAC processor with integrated SHA-1 and MD5 algorithms.
ASP-DAC 2004: 456-458 |
| 3 | EE | Chih-Pin Su,
Cheng-Wen Wu:
A Graph-Based Approach to Power-Constrained SOC Test Scheduling.
J. Electronic Testing 20(1): 45-60 (2004) |
| 2002 |
|---|
| 2 | EE | Jin-Fu Li,
Hsin-Jung Huang,
Jeng-Bin Chen,
Chih-Pin Su,
Cheng-Wen Wu,
Chuang Cheng,
Shao-I Chen,
Chi-Yi Hwang,
Hsiao-Ping Lin:
A Hierarchical Test Scheme for System-On-Chip Designs.
DATE 2002: 486-490 |
| 1 | EE | Jin-Fu Li,
Hsin-Jung Huang,
Jeng-Bin Chen,
Chih-Pin Su,
Cheng-Wen Wu,
Chuang Cheng,
Shao-I Chen,
Chi-Yi Hwang,
Hsiao-Ping Lin:
A Hierarchical Test Methodology for Systems on Chip.
IEEE Micro 22(5): 69-81 (2002) |
