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D. J. Soudris
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
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101 | EE | Alexandros Bartzas, Miguel Peon-Quiros, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias: Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information. ASP-DAC 2008: 434-439 |
100 | EE | Kostas Siozios, Dimitrios Soudris: An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs. PATMOS 2008: 439-448 |
99 | EE | Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris: Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms. Journal of Systems Architecture - Embedded Systems Design 54(11): 1030-1038 (2008) |
2007 | ||
98 | EE | Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis: Designing Heterogeneous FPGAs with Multiple SBs. ARC 2007: 91-96 |
97 | EE | Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor: Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns. DATE 2007: 1036-1041 |
96 | EE | Christos Baloukas, Lazaros Papadopoulos, Stylianos Mamagkakis, Dimitrios Soudris: Component Based Library Implementation of Abstract Data Types for Resource Management Customization of Embedded Systems. ESTImedia 2007: 99-104 |
95 | EE | Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris: Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support. FPL 2007: 652-655 |
94 | EE | Lazaros Papadopoulos, Christos Baloukas, Nikolaos Zompakis, Dimitrios Soudris: Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems. ICSAMOS 2007: 58-65 |
93 | EE | Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris: Application - specific NoC platform design based on System Level Optimization. ISVLSI 2007: 311-316 |
92 | EE | Kostas Siozios, Dimitrios Soudris: A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs. ISVLSI 2007: 55-60 |
91 | EE | Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, N. Voros: Data Structure Exploration of Dynamic Applications. PACT 2007: 421 |
90 | EE | Lazaros Papadopoulos, Dimitrios Soudris: System-Level Application-Specific NoC Design for Network and Multimedia Applications. PATMOS 2007: 1-9 |
89 | EE | Miguel Peon-Quiros, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris: Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption. PATMOS 2007: 373-383 |
88 | EE | Nikolas Kroupis, Dimitrios Soudris: Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate. PATMOS 2007: 505-515 |
87 | EE | David Atienza, Christos Baloukas, Lazaros Papadopoulos, Christophe Poucet, Stylianos Mamagkakis, José Ignacio Hidalgo, Francky Catthoor, Dimitrios Soudris, Juan Lanchares: Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation. SCOPES 2007: 31-40 |
86 | EE | Nikolaos Zompakis, Lazaros Papadopoulos, Georgios Ch. Sirakoulis, Dimitrios Soudris: Implementing cellular automata modeled applications on network-on-chip platforms. VLSI-SoC 2007: 288-291 |
85 | EE | Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris: A software-supported methodology for designing high-performance 3D FPGA architectures. VLSI-SoC 2007: 54-59 |
84 | EE | Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck CoRR abs/0710.4656: (2007) |
83 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms CoRR abs/0710.4844: (2007) |
82 | EE | Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru: Preface. Integration 40(2): 61 (2007) |
81 | EE | Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis: Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. Integration 40(2): 74-93 (2007) |
80 | EE | Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. Journal of Systems Architecture 53(7): 417-436 (2007) |
79 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. Microprocessors and Microsystems 31(1): 1-14 (2007) |
2006 | ||
78 | EE | Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. DATE 2006: 740-745 |
77 | EE | Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias: Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems. DATE 2006: 874-875 |
76 | EE | Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris: Energy-efficient dynamic memory allocators at the middleware level of embedded systems. EMSOFT 2006: 215-222 |
75 | EE | Nikolas Kroupis, Stylianos Mamagkakis, Dimitrios Soudris: An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems. ESTImedia 2006: 21-26 |
74 | EE | K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis: A novel methodology for designing high-performance and low-energy FPGA routing architecture. FPGA 2006: 224 |
73 | EE | Kostas Siozios, Dimitrios Soudris: Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures. FPL 2006: 1-4 |
72 | EE | Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. IPDPS 2006 |
71 | EE | Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis: A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. ISCAS 2006 |
70 | EE | Alexandros Bartzas, M. Peón, Stylianos Mamagkakis, David Atienza, Francky Catthoor, Dimitrios Soudris, M. Mendias: Systematic design flow for dynamic data management in visual texture decoder of MPEG-4. ISCAS 2006 |
69 | EE | Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. PATMOS 2006: 403-414 |
68 | EE | Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. VLSI-SoC 2006: 204-209 |
67 | EE | David Atienza, Jose Manuel Mendias, Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor: Systematic dynamic memory management design methodology for reduced memory footprint. ACM Trans. Design Autom. Electr. Syst. 11(2): 465-489 (2006) |
66 | EE | Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance. Computer Communications 29(13-14): 2612-2620 (2006) |
65 | EE | Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis: A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. IEEE Trans. VLSI Syst. 14(3): 279-291 (2006) |
64 | EE | David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris: Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems. Integration 39(2): 113-130 (2006) |
63 | EE | Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris: Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers. J. Low Power Electronics 2(3): 356-364 (2006) |
62 | EE | Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. VLSI Signal Processing 44(1-2): 153-171 (2006) |
2005 | ||
61 | EE | Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, K. Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis: AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. ASP-DAC 2005: 3-4 |
60 | EE | Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. DATE 2005: 946-947 |
59 | K. Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis: An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL 2005: 658-661 | |
58 | K. Siozios, Dimitrios Soudris, Adonios Thanailakis: A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. FPL 2005: 707-708 | |
57 | Nikolas Kroupis, Minas Dasygenis, Dimitrios Soudris, Antonios Thanailakis: A Modified Spiral Search Algorithm and its Embedded Hardware Implementation. IEC (Prague) 2005: 375-378 | |
56 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. IPDPS 2005 |
55 | EE | K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. IPDPS 2005 |
54 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A methodology for partitioning DSP applications in hybrid reconfigurable systems. ISCAS (2) 2005: 1206-1209 |
53 | EE | Nikolas Kroupis, Minas Dasygenis, K. Markou, Dimitrios Soudris, Adonios Thanailakis: A modified spiral search motion estimation algorithm and its embedded system implementation. ISCAS (4) 2005: 3347-3350 |
52 | EE | Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Improving the Memory Bandwidth Utilization Using Loop Transformations. PATMOS 2005: 117-126 |
51 | EE | Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis: Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. WWIC 2005: 354-364 |
50 | EE | Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos: A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. IEICE Transactions 88-D(7): 1369-1380 (2005) |
49 | EE | Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms. J. Embedded Computing 1(3): 353-362 (2005) |
48 | EE | Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis: A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. Journal of Circuits, Systems, and Computers 14(2): 281-296 (2005) |
47 | EE | Nikolaos D. Zervas, George Theodoridis, Dimitrios Soudris: Behavioral-level event-driven power management for DECT digital receivers. Microelectronics Journal 36(2): 163-172 (2005) |
46 | EE | Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, Ilias Pappas, George Koutroumpezis, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris: A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. Microprocessors and Microsystems 29(6): 247-259 (2005) |
2004 | ||
45 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. DATE 2004: 247-252 |
44 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. DATE 2004: 247-252 |
43 | EE | David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris: Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications. DATE 2004: 532-537 |
42 | David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris: Reducing memory accesses with a system-level design methodology in customized dynamic memory management. ESTImedia 2004: 93-98 | |
41 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis: Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. FCCM 2004: 275-276 |
40 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis: A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. FPGA 2004: 252 |
39 | EE | K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. FPL 2004: 1116-1118 |
38 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis: Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. FPL 2004: 868-873 |
37 | EE | Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis: An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS 2004 |
36 | EE | Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis: A reusable IP FFT core for DSP applications. ISCAS (3) 2004: 621-624 |
35 | EE | David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris: Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems. PATMOS 2004: 510-520 |
34 | EE | Kostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis: Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform. PATMOS 2004: 613-622 |
33 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis: Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. PATMOS 2004: 652-661 |
32 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis: A Novel Data-Path for Accelerating DSP Kernels. SAMOS 2004: 363-372 |
31 | EE | Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. SAMOS 2004: 540-549 |
30 | EE | Stylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis: Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. WWIC 2004: 26-37 |
29 | EE | Christos Drosos, Chrissavgi Dre, Dimitris Metafas, Dimitrios Soudris, Spyros Blionas: The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal. Microelectronics Journal 35(7): 609-620 (2004) |
2003 | ||
28 | EE | Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis: Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. FPL 2003: 1032-1035 |
27 | EE | Dimitrios Soudris, Marios Kesoulis, C. Koukourlis, Adonios Thanailakis, Spyros Blionas: Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. ISCAS (2) 2003: 73-76 |
26 | EE | Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis: A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ISCAS (5) 2003: 129-132 |
25 | EE | Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas: Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS 2003: 430-439 |
24 | EE | Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis: FPGA Architecture Design and Toolset for Logic Implementation. PATMOS 2003: 607-616 |
23 | Marios Kesoulis, Dimitrios Soudris, C. Koukourlis, Adonios Thanailakis: Designing Low Power Direct Digital Frequency Synthesizers. VLSI-SOC 2003: 105-110 | |
22 | EE | Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. Real-Time Imaging 9(6): 371-386 (2003) |
2002 | ||
21 | EE | Nikolaos D. Liveris, Nikolaos D. Zervas, Dimitrios Soudris, Constantinos E. Goutis: A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications. DATE 2002: 977-983 |
20 | EE | George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis: Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. FPL 2002: 1027-1036 |
19 | Antonios Atsalakis, Nikos Papamarkos, Dimitrios Soudris, Nikolas Kroupis: A window-based color quantization technique and its embedded implementation. ICIP (2) 2002: 365-368 | |
18 | EE | Athanasios Kakarountas, K. Papadomanolakis, Spiridon Nikolaidis, Dimitrios Soudris, Constantinos E. Goutis: Confronting violations of the TSCG(T) in low-power design. ISCAS (4) 2002: 313-316 |
17 | EE | Nikolaos D. Zervas, G. Pagkless, Minas Dasygenis, Dimitrios Soudris: Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors. PATMOS 2002: 323-331 |
16 | EE | S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis: A fast and accurate delay dependent method for switching estimation of large combinational circuits. Journal of Systems Architecture 48(4-5): 113-124 (2002) |
2001 | ||
15 | EE | Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis: Power, performance and area exploration of block matching algorithms mapped on programmable processors. ICIP (3) 2001: 728-731 |
14 | EE | Nikolaos D. Zervas, I. Tagopoulos, Vassilis Spiliotopoulos, Giorgos P. Anagnostopoulos, Dimitrios Soudris, Constantinos E. Goutis: Performance comparison of DWT scheduling alternatives on programmable platforms. ISCAS (2) 2001: 761-764 |
13 | EE | I. Thoidis, Dimitrios Soudris, J. M. Fernandez, Adonios Thanailakis: The circuit design of multiple-valued logic voltage-mode adders. ISCAS (4) 2001: 162-165 |
12 | EE | Christos Drosos, Chrissavgi Dre, Spyros Blionas, Dimitrios Soudris: On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal. ISCAS (4) 2001: 334-337 |
11 | EE | D. J. Soudris, M. M. Dasigenis, S. K. Vasilopoulou, Adonios Thanailakis: A CAD tool for architecture level exploration and automatic generation of RNS converters. ISCAS (4) 2001: 730-733 |
10 | EE | Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas: Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. ISQED 2001: 456-461 |
2000 | ||
9 | Dimitrios Soudris, Peter Pirsch, Erich Barke: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings Springer 2000 | |
8 | EE | Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis: Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. PATMOS 2000: 243-254 |
7 | EE | Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. PATMOS 2000: 47-55 |
1999 | ||
6 | EE | M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, G. A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis: The VLSI implementation of a baseband receiver for DECT-based portable applications. ISCAS (1) 1999: 198-201 |
5 | EE | George Theodoridis, S. Theoharis, Dimitrios Soudris, Thanos Stouraitis, Constantinos E. Goutis: An efficient probabilistic method for logic circuits using real delay gate model. ISCAS (1) 1999: 286-289 |
1998 | ||
4 | EE | I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis: Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. Great Lakes Symposium on VLSI 1998: 83-88 |
1993 | ||
3 | Dimitrios Soudris, P. D. Georgakopoulos, Constantinos E. Goutis: A Systematic Methodology for Designing Multilevel Systolic Architectures. ISCAS 1993: 1738-1741 | |
2 | Vassilis Paliouras, Dimitrios Soudris, Thanos Stouraitis: Methodology for the Design of Signed-digit DSP Processors. ISCAS 1993: 1833-1836 | |
1991 | ||
1 | Dimitrios Soudris, Michael K. Birbas, Constantinos E. Goutis: Direct mapping of nested loops on piecewise regular processor arrays. Algorithms and Parallel VLSI Architectures 1991: 145-150 |