| 2009 |
|---|
| 105 | EE | Xiaojun Ma,
Jing Huang,
Cecilia Metra,
Fabrizio Lombardi:
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates.
J. Electronic Testing 25(1): 39-54 (2009) |
| 2008 |
|---|
| 104 | EE | Cecilia Metra,
Martin Omaña,
T. M. Mak,
Asifur Rahman,
Simon Tam:
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors.
DFT 2008: 465-473 |
| 103 | EE | Daniele Rossi,
André K. Nieuwland,
Cecilia Metra:
Simultaneous Switching Noise: The Relation between Bus Layout and Coding.
IEEE Design & Test of Computers 25(1): 76-86 (2008) |
| 102 | EE | Daniele Rossi,
André K. Nieuwland,
Steven V. E. S. van Dijk,
Richard P. Kleihorst,
Cecilia Metra:
Power Consumption of Fault Tolerant Busses.
IEEE Trans. VLSI Syst. 16(5): 542-553 (2008) |
| 101 | EE | Xiaojun Ma,
Jing Huang,
Cecilia Metra,
Fabrizio Lombardi:
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA.
J. Electronic Testing 24(1-3): 297-311 (2008) |
| 100 | EE | Daniele Rossi,
Martin Omaña,
Cecilia Metra:
Checkers' No-Harm Alarms and Design Approaches to Tolerate Them.
J. Electronic Testing 24(1-3): 93-103 (2008) |
| 2007 |
|---|
| 99 | EE | Michele Favalli,
Cecilia Metra:
Interactive presentation: Pulse propagation for the detection of small delay defects.
DATE 2007: 1295-1300 |
| 98 | EE | Jing Huang,
Xiaojun Ma,
Cecilia Metra,
Fabrizio Lombardi:
Testing Reversible One-Dimensional QCA Arrays for Multiple Faults.
DFT 2007: 469-477 |
| 97 | EE | Daniele Rossi,
Paolo Angelini,
Cecilia Metra:
Configurable Error Control Scheme for NoC Signal Integrity.
IOLTS 2007: 43-48 |
| 96 | EE | Cecilia Metra,
Martin Omaña,
T. M. Mak,
Simon Tam:
Novel Approach to Clock Fault Testing for High Performance Microprocessors.
VTS 2007: 441-446 |
| 95 | EE | Fabrizio Lombardi,
Cecilia Metra:
Guest Editors' Introduction: The State of the Art in Nanoscale CAD.
IEEE Design & Test of Computers 24(4): 302-303 (2007) |
| 94 | EE | Cecilia Metra,
Daniele Rossi,
T. M. Mak:
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?.
IEEE Trans. Computers 56(3): 415-428 (2007) |
| 93 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Latch Susceptibility to Transient Faults and New Hardening Approach.
IEEE Trans. Computers 56(9): 1255-1268 (2007) |
| 2006 |
|---|
| 92 | EE | Martin Omaña,
José Manuel Cazeaux,
Daniele Rossi,
Cecilia Metra:
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects.
DATE 2006: 170-175 |
| 91 | EE | Daniele Rossi,
Carlo Steiner,
Cecilia Metra:
Analysis of the impact of bus implemented EDCs on on-chip SSN.
DATE 2006: 59-64 |
| 90 | | Cecilia Metra,
Daniele Rossi,
Martin Omaña,
José Manuel Cazeaux,
T. M. Mak:
Can Clock Faults be Detected Through Functional Test?
DDECS 2006: 168-173 |
| 89 | EE | Xiaojun Ma,
Jing Huang,
Cecilia Metra,
Fabrizio Lombardi:
Testing Reversible 1D Arrays for Molecular QCA.
DFT 2006: 71-79 |
| 88 | EE | Cecilia Metra,
Martin Omaña,
Daniele Rossi,
José Manuel Cazeaux,
T. M. Mak:
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.
IOLTS 2006: 17-22 |
| 87 | EE | Daniele Rossi,
Martin Omaña,
Cecilia Metra,
Andrea Pagni:
Checker No-Harm Alarm Robustness.
IOLTS 2006: 275-280 |
| 86 | EE | Jien-Chung Lo,
Cecilia Metra,
Fabrizio Lombardi:
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC).
IEEE Trans. Computers 55(2): 97-98 (2006) |
| 2005 |
|---|
| 85 | EE | Cecilia Metra,
Martin Omaña,
Daniele Rossi,
José Manuel Cazeaux,
T. M. Mak:
The Other Side of the Timing Equation: a Result of Clock Faults.
DFT 2005: 169-177 |
| 84 | EE | Daniele Rossi,
Martin Omaña,
Fabio Toma,
Cecilia Metra:
Multiple Transient Faults in Logic: An Issue for Next Generation ICs.
DFT 2005: 352-360 |
| 83 | EE | Martin Omaña,
O. Losco,
Cecilia Metra,
Andrea Pagni:
On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization.
IOLTS 2005: 163-168 |
| 82 | EE | André K. Nieuwland,
Atul Katoch,
Daniele Rossi,
Cecilia Metra:
Coding Techniques for Low Switching Noise in Fault Tolerant Busses.
IOLTS 2005: 183-189 |
| 81 | EE | José Manuel Cazeaux,
Daniele Rossi,
Martin Omaña,
Cecilia Metra,
Abhijit Chatterjee:
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.
IOLTS 2005: 23-28 |
| 80 | EE | Yuvraj Singh Dhillon,
Abdulkadir Utku Diril,
Abhijit Chatterjee,
Cecilia Metra:
Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits.
IOLTS 2005: 35-40 |
| 79 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Low Cost Scheme for On-Line Clock Skew Compensation.
VTS 2005: 90-95 |
| 78 | EE | Daniele Rossi,
André K. Nieuwland,
Atul Katoch,
Cecilia Metra:
Exploiting ECC Redundancy to Minimize Crosstalk Impact.
IEEE Design & Test of Computers 22(1): 59-70 (2005) |
| 77 | EE | Daniele Rossi,
André K. Nieuwland,
Atul Katoch,
Cecilia Metra:
New ECC for Crosstalk Impact Minimization.
IEEE Design & Test of Computers 22(4): 340-348 (2005) |
| 76 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Low Cost and High Speed Embedded Two-Rail Code Checker.
IEEE Trans. Computers 54(2): 153-164 (2005) |
| 75 | EE | José Manuel Cazeaux,
Daniele Rossi,
Cecilia Metra:
Self-Checking Voter for High Speed TMR Systems.
J. Electronic Testing 21(4): 377-389 (2005) |
| 2004 |
|---|
| 74 | EE | Cecilia Metra,
T. M. Mak,
Martin Omaña:
Fault secureness need for next generation high performance microprocessor design for testability structures.
Conf. Computing Frontiers 2004: 444-450 |
| 73 | EE | Cecilia Metra,
T. M. Mak,
Martin Omaña:
Are Our Design for Testability Features Fault Secure?
DATE 2004: 714-715 |
| 72 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Fast and Low-Cost Clock Deskew Buffer.
DFT 2004: 202-210 |
| 71 | EE | Daniele Rossi,
A. Muccio,
André K. Nieuwland,
Atul Katoch,
Cecilia Metra:
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems.
IOLTS 2004: 135-140 |
| 70 | EE | Cecilia Metra,
A. Ferrari,
Martin Omaña,
Andrea Pagni:
Hardware Reconfiguration Scheme for High Availability Systems.
IOLTS 2004: 161-166 |
| 69 | EE | José Manuel Cazeaux,
Martin Omaña,
Cecilia Metra:
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.
IOLTS 2004: 17-24 |
| 68 | EE | José Manuel Cazeaux,
Daniele Rossi,
Cecilia Metra:
New High Speed CMOS Self-Checking Voter.
IOLTS 2004: 58-66 |
| 67 | EE | Cecilia Metra,
T. M. Mak,
Martin Omaña:
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing.
ITC 2004: 1223-1231 |
| 66 | EE | André Ivanov,
Fabrizio Lombardi,
Cecilia Metra:
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates.
IEEE Design & Test of Computers 21(4): 274-276 (2004) |
| 65 | EE | Cecilia Metra,
Stefano Di Francescantonio,
T. M. Mak:
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing.
IEEE Trans. Computers 53(5): 531-546 (2004) |
| 64 | EE | Michele Favalli,
Cecilia Metra:
TMR voting in the presence of crosstalk faults at the voter inputs.
IEEE Transactions on Reliability 53(3): 342-348 (2004) |
| 63 | EE | Cecilia Metra,
Matteo Sonza Reorda:
Guest Editorial.
J. Electronic Testing 20(5): 463 (2004) |
| 62 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Model for Transient Fault Susceptibility of Combinational Circuits.
J. Electronic Testing 20(5): 501-509 (2004) |
| 2003 |
|---|
| 61 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
High Speed and Highly Testable Parallel Two-Rail Code Checker.
DATE 2003: 10608-10615 |
| 60 | EE | Daniele Rossi,
S. Cavallotti,
Cecilia Metra:
Error Correcting Codes for Crosstalk Effect Minimization.
DFT 2003: 257- |
| 59 | EE | Cecilia Metra,
Stefano Di Francescantonio,
Martin Omaña:
Automatic Modification of Sequential Circuits for Self-Checking Implementation.
DFT 2003: 417-424 |
| 58 | EE | Cecilia Metra,
T. M. Mak,
Daniele Rossi:
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors.
DFT 2003: 63-70 |
| 57 | EE | Martin Omaña,
Giacinto Papasso,
Daniele Rossi,
Cecilia Metra:
A Model for Transient Fault Propagation in Combinatorial Logic.
IOLTS 2003: 111- |
| 56 | EE | L. Di Silvio,
Daniele Rossi,
Cecilia Metra:
Crosstalk Effect Minimization for Encoded Busses.
IOLTS 2003: 214-218 |
| 55 | EE | Daniele Rossi,
Steven V. E. S. van Dijk,
Richard P. Kleihorst,
André K. Nieuwland,
Cecilia Metra:
Power Consumption of Fault Tolerant Codes: the Active Elements.
IOLTS 2003: 61-67 |
| 54 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Novel Transient Fault Hardened Static Latch.
ITC 2003: 886-892 |
| 53 | EE | Cecilia Metra,
Luca Schiano,
Michele Favalli:
Concurrent detection of power supply noise.
IEEE Transactions on Reliability 52(4): 469-475 (2003) |
| 52 | EE | Cecilia Metra,
Matteo Sonza Reorda:
Guest Editorial.
J. Electronic Testing 19(5): 499 (2003) |
| 51 | EE | Daniele Rossi,
Cecilia Metra:
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories.
J. Electronic Testing 19(5): 511-521 (2003) |
| 50 | EE | Cecilia Metra,
Stefano Di Francescantonio,
Michele Favalli,
Bruno Riccò:
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults.
Microelectronics Journal 34(1): 23-29 (2003) |
| 2002 |
|---|
| 49 | EE | Michele Favalli,
Cecilia Metra:
Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths.
DATE 2002: 612-619 |
| 48 | EE | Cecilia Metra,
Luca Schiano,
Bruno Riccò,
Michele Favalli:
Self-Checking Scheme for the On-Line Testing of Power Supply Noise.
DATE 2002: 832-836 |
| 47 | EE | Cecilia Metra,
Stefano Di Francescantonio,
Giuseppe Marrale:
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits.
DFT 2002: 207-215 |
| 46 | EE | Daniele Rossi,
Cecilia Metra,
Bruno Riccò:
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories.
IOLTW 2002: 221-225 |
| 45 | EE | Luca Schiano,
Cecilia Metra,
Diego Marino:
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems.
IOLTW 2002: 243- |
| 44 | EE | Daniele Rossi,
Steven V. E. S. van Dijk,
Richard P. Kleihorst,
A. H. Nieuwland,
Cecilia Metra:
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus.
IOLTW 2002: 8-12 |
| 43 | EE | Cecilia Metra,
Stefano Di Francescantonio,
T. M. Mak:
Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing.
ITC 2002: 100-109 |
| 42 | EE | Daniele Rossi,
Cecilia Metra,
Bruno Riccò:
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories.
MTDT 2002: 27-31 |
| 41 | EE | Luca Schiano,
Cecilia Metra,
Diego Marino:
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems.
MTDT 2002: 49-56 |
| 40 | EE | Michele Favalli,
Cecilia Metra:
Online Testing Approach for Very Deep-Submicron ICs.
IEEE Design & Test of Computers 19(2): 16-23 (2002) |
| 39 | EE | Dimitris Nikolos,
John P. Hayes,
Michael Nicolaidis,
Cecilia Metra:
Guest Editorial.
J. Electronic Testing 18(3): 259-260 (2002) |
| 38 | EE | Michele Favalli,
Cecilia Metra:
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures.
J. Electronic Testing 18(3): 273-283 (2002) |
| 37 | EE | Cecilia Metra,
Michele Favalli,
Stefano Di Francescantonio,
Bruno Riccò:
On-Chip Clock Faults' Detector.
J. Electronic Testing 18(4-5): 555-564 (2002) |
| 2001 |
|---|
| 36 | EE | Michele Favalli,
Cecilia Metra:
Optimization of error detecting codes for the detection of crosstalk originated errors.
DATE 2001: 290-296 |
| 35 | EE | Cecilia Metra,
Stefano Di Francescantonio,
Bruno Riccò,
T. M. Mak:
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects.
DFT 2001: 357-365 |
| 34 | EE | Michele Favalli,
Cecilia Metra:
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures.
IOLTW 2001: 100-105 |
| 33 | EE | Monica Alderighi,
Sergio D'Angelo,
Giacomo R. Sechi,
Cecilia Metra:
Novel Fault-Tolerant Adder Design for FPGA-Based Systems.
IOLTW 2001: 54- |
| 32 | | Cecilia Metra,
Andrea Pagano,
Bruno Riccò:
On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems.
ITC 2001: 939-947 |
| 31 | | Fabrizio Lombardi,
Cecilia Metra:
Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems.
IEEE Design & Test of Computers 18(1): 8-9 (2001) |
| 2000 |
|---|
| 30 | EE | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values.
DATE 2000: 763 |
| 29 | EE | Monica Alderighi,
Sergio D'Angelo,
Giacomo R. Sechi,
Cecilia Metra:
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs.
DFT 2000: 155-163 |
| 28 | EE | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines.
IEEE Trans. Computers 49(6): 560-574 (2000) |
| 27 | EE | Cecilia Metra,
Jien-Chung Lo:
Intermediacy Prediction for High Speed Berger Code Checkers.
J. Electronic Testing 16(6): 607-615 (2000) |
| 26 | EE | Michele Favalli,
Cecilia Metra:
Bridging Faults in Pipelined Circuits.
J. Electronic Testing 16(6): 617-629 (2000) |
| 1999 |
|---|
| 25 | EE | Michele Favalli,
Cecilia Metra:
On the Design of Self-Checking Functional Units Based on Shannon Circuits.
DATE 1999: 368-375 |
| 24 | EE | Sergio D'Angelo,
Giacomo R. Sechi,
Cecilia Metra:
Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems.
DFT 1999: 330-338 |
| 23 | | Cecilia Metra,
Flavio Giovanelli,
Mani Soma,
Bruno Riccò:
Self-checking scheme for very fast clocks' skew correction.
ITC 1999: 652-661 |
| 22 | EE | Michele Favalli,
Cecilia Metra:
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing.
IEEE Trans. VLSI Syst. 7(3): 392-396 (1999) |
| 1998 |
|---|
| 21 | EE | Cecilia Metra,
Michel Renovell,
G. Mojoli,
Jean Michel Portal,
Sandro Pastore,
Joan Figueras,
Yervant Zorian,
Davide Salvi,
Giacomo R. Sechi:
Novel Technique for Testing FPGAs.
DATE 1998: 89- |
| 20 | EE | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
Highly Testable and Compact 1-out-of-n Code Checker with Single Output.
DATE 1998: 981-982 |
| 19 | EE | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks.
DFT 1998: 174-182 |
| 18 | EE | Sergio D'Angelo,
Cecilia Metra,
Sandro Pastore,
A. Pogutz,
Giacomo R. Sechi:
Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems.
DFT 1998: 233-240 |
| 17 | EE | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
On-line detection of logic errors due to crosstalk, delay, and transient faults.
ITC 1998: 524-533 |
| 16 | EE | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
Concurrent Checking of Clock Signal Correctness.
IEEE Design & Test of Computers 15(4): 42-48 (1998) |
| 1997 |
|---|
| 15 | EE | Yu-Yau Guo,
Jien-Chung Lo,
Cecilia Metra:
Fast and area-time efficient Berger code checkers.
DFT 1997: 110-118 |
| 14 | EE | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
Compact and low power on-line self-testing voting scheme.
DFT 1997: 137-147 |
| 13 | EE | Michele Favalli,
Cecilia Metra:
Low-level error recovery mechanism for self-checking sequential circuits.
DFT 1997: 234-242 |
| 12 | EE | Michele Favalli,
Cecilia Metra:
Testing scheme for IC's clocks.
ED&TC 1997: 445-449 |
| 11 | | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
On-Line Testing Scheme for Clock's Faults.
ITC 1997: 587-596 |
| 10 | EE | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
Highly testable and compact single output comparator.
VTS 1997: 210-215 |
| 9 | EE | Cecilia Metra,
Michele Favalli,
Piero Olivo,
Bruno Riccò:
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 770-776 (1997) |
| 1996 |
|---|
| 8 | EE | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
Embedded two-rail checkers with on-line testing ability.
VTS 1996: 145-150 |
| 7 | EE | Michele Favalli,
Cecilia Metra:
Sensing circuit for on-line detection of delay faults.
IEEE Trans. VLSI Syst. 4(1): 130-133 (1996) |
| 1995 |
|---|
| 6 | EE | Cecilia Metra,
Michele Favalli,
Piero Olivo,
Bruno Riccò:
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults.
J. Electronic Testing 6(1): 7-22 (1995) |
| 1994 |
|---|
| 5 | | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
CMOS Self Checking Circuits with Faulty Sequential Functional Block.
DFT 1994: 133-141 |
| 4 | | Cecilia Metra,
Michele Favalli,
Bruno Riccò:
Highly Testable and Compact 1-out-of-n CMOS Checkers.
DFT 1994: 142-150 |
| 1993 |
|---|
| 3 | | Cecilia Metra,
Michele Favalli,
Piero Olivo,
Bruno Riccò:
Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block.
DFT 1993: 271-278 |
| 2 | | Cecilia Metra,
Michele Favalli,
Piero Olivo,
Bruno Riccò:
A Highly Testable 1-out-of-3 CMOS Checker.
DFT 1993: 279-286 |
| 1992 |
|---|
| 1 | | Cecilia Metra,
Michele Favalli,
Piero Olivo,
Bruno Riccò:
CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults.
ITC 1992: 948-957 |
