2008 | ||
---|---|---|
41 | EE | Cong Liu, Alex Kondratyev, Yosinori Watanabe, Jörg Desel, Alberto L. Sangiovanni-Vincentelli: Schedulability Analysis of Petri Nets Based on Structural Properties. Fundam. Inform. 86(3): 325-341 (2008) |
2006 | ||
40 | EE | Shinjiro Kakita, Yosinori Watanabe, Douglas Densmore, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli: Functional Model Exploration for Multimedia Applications via Algebraic Operators. ACSD 2006: 229-238 |
39 | EE | Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli, Jörg Desel: Schedulability Analysis of Petri Nets Based on Structural Properties. ACSD 2006: 69-78 |
2005 | ||
38 | EE | Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe: Simulation based deadlock analysis for system level designs. DAC 2005: 260-265 |
37 | EE | Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe: A Time Slice Based Scheduler Model for System Level Design. DATE 2005: 378-383 |
36 | EE | Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli: A structural approach to quasi-static schedulability analysis of communicating concurrent programs. EMSOFT 2005: 10-16 |
35 | EE | Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe: Quasi-static scheduling of independent tasks for reactive systems. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1492-1514 (2005) |
34 | EE | Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska: Eliminating false positives in crosstalk noise analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1406-1419 (2005) |
33 | EE | Gianpiero Cabodi, Alex Kondratyev, Luciano Lavagno, Sergio Nocco, Stefano Quer, Yosinori Watanabe: A BMC-based formulation for the scheduling problem of hardware systems. STTT 7(2): 102-117 (2005) |
2004 | ||
32 | EE | Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska: Eliminating False Positives in Crosstalk Noise Analysis. DATE 2004: 1192-1197 |
31 | EE | Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin: Separation of concerns: overhead in modeling and efficient simulation techniques. EMSOFT 2004: 44-53 |
30 | EE | Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Yosinori Watanabe: Quasi-static Scheduling for Concurrent Architectures. Fundam. Inform. 62(2): 171-196 (2004) |
29 | EE | Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe: Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1243-1255 (2004) |
2003 | ||
28 | EE | Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe: Case Studies of Model Checking for Embedded System Designs. ACSD 2003: 20-28 |
27 | EE | Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe: Quasi-Static Scheduling for Concurrent Architectures. ACSD 2003: 29-40 |
26 | EE | Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe: Automatic trace analysis for logic of constraints. DAC 2003: 460-465 |
25 | EE | Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska: Gain-based technology mapping for discrete-size cell libraries. DAC 2003: 574-579 |
24 | EE | Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska: Temporofunctional crosstalk noise analysis. DAC 2003: 860-863 |
23 | EE | Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev: An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. DATE 2003: 10428-10435 |
22 | EE | Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe: Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE 2003: 11174-11175 |
21 | EE | Gianpiero Cabodi, Sergio Nocco, Stefano Quer, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe: A BMC-formulation for the scheduling problem in highly constrained hardware Systems. Electr. Notes Theor. Comput. Sci. 89(4): (2003) |
20 | EE | Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli: Metropolis: An Integrated Electronic System Design Environment. IEEE Computer 36(4): 45-52 (2003) |
2002 | ||
19 | EE | Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang: Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. CODES 2002: 13-18 |
18 | EE | Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe: Modeling and Designing Heterogeneous Systems. Concurrency and Hardware Design 2002: 228-273 |
17 | EE | G. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe: False Path Elimination in Quasi-Static Scheduling. DATE 2002: 964-970 |
16 | EE | Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe: Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. EMSOFT 2002: 407-416 |
15 | EE | Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe: Quasi-Static Scheduling of Independent Tasksfor Reactive Systems. ICATPN 2002: 80-100 |
2001 | ||
14 | EE | Claudio Passerone, Yosinori Watanabe, Luciano Lavagno: Generation of minimal size code for scheduling graphs. DATE 2001: 668-673 |
2000 | ||
13 | EE | Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli: Task generation and compile-time scheduling for mixed data-control embedded software. DAC 2000: 489-494 |
12 | EE | Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten: Area and search space control for technology mapping. DAC 2000: 86-91 |
1999 | ||
11 | EE | H. J. H. N. Kenter, Claudio Passerone, W. J. M. Smits, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli: Designing digital video systems: modeling and scheduling. CODES 1999: 64-68 |
10 | EE | Marco Sgroi, Luciano Lavagno, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli: Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets. ICATPN 1999: 208-227 |
1996 | ||
9 | EE | Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton: Permissible functions for multioutput components in combinational logic optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 732-744 (1996) |
1995 | ||
8 | EE | Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness: Logic decomposition during technology mapping. ICCAD 1995: 264-271 |
1994 | ||
7 | Yosinori Watanabe, Robert K. Brayton: State Minimization of Pseudo Non-Deterministic FSM's. EDAC-ETC-EUROASIC 1994: 184-191 | |
1993 | ||
6 | EE | Yosinori Watanabe, Robert K. Brayton: The maximum set of permissible behaviors for FSM networks. ICCAD 1993: 316-320 |
5 | Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton: Logic Optimization with Multi-Output Gates. ICCD 1993: 416-420 | |
4 | Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton: Heuristic Minimization of Synchronous Relations. ICCD 1993: 428-433 | |
3 | EE | Yosinori Watanabe, Robert K. Brayton: Heuristic minimization of multiple-valued relations. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1458-1472 (1993) |
1991 | ||
2 | Yosinori Watanabe, Robert K. Brayton: Heuristic Minimazation of Multiple-Valued Relations. ICCAD 1991: 126-129 | |
1 | Yosinori Watanabe, Robert K. Brayton: Incremental Synthesis for Engineering Changes. ICCD 1991: 40-43 |