Juan Lanchares

2008
35	EE	José L. Risco-Martín, José Ignacio Hidalgo, Juan Lanchares, Oscar Garnica: Solving discrete deceptive problems with EMMRS. GECCO 2008: 1139-1140
34	EE	José Ignacio Hidalgo, José L. Risco-Martín, David Atienza, Juan Lanchares: Analysis of multi-objective evolutionary algorithms to optimize dynamic data types in embedded systems. GECCO 2008: 1515-1522
33	EE	José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo: Modelling Asynchronous Systems using Probability Distribution Functions. PDP 2008: 3-11
32	EE	José L. Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares: A parallel evolutionary algorithm to optimize dynamic data types in embedded systems. Soft Comput. 12(12): 1157-1167 (2008)
2007
31	EE	José Ignacio Hidalgo, Francisco Fernández de Vega, Juan Lanchares, Daniel Lombraña Gonzalez: Is the island model fault tolerant? GECCO 2007: 1519
30	EE	José Ignacio Hidalgo, Juan Lanchares, Francisco Fernández de Vega, Daniel Lombraña Gonzalez: Is the island model fault tolerant? GECCO (Companion) 2007: 2737-2744
29	EE	Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares: Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. HiPEAC 2007: 136-150
28	EE	Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares: Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. PACT 2007: 416
27	EE	David Atienza, Christos Baloukas, Lazaros Papadopoulos, Christophe Poucet, Stylianos Mamagkakis, José Ignacio Hidalgo, Francky Catthoor, Dimitrios Soudris, Juan Lanchares: Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation. SCOPES 2007: 31-40
2006
26	EE	José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López: Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. DSD 2006: 423-432
25	EE	Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar: A Power-Aware Technique for Functional Units in High-Performance Processors. DSD 2006: 456-459
24	EE	José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López: Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par 2006: 495-505
23	EE	Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López: A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. PATMOS 2006: 514-523
2005
22	EE	Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar: Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. PATMOS 2005: 40-48
2004
21	EE	José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida: Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP 2004: 112-119
20	EE	Juan de Vicente, Juan Lanchares, Román Hermida: Annealing placement by thermodynamic combinatorial optimization. ACM Trans. Design Autom. Electr. Syst. 9(3): 310-332 (2004)
19	EE	Francisco Fernández, José Ignacio Hidalgo, Juan Lanchares, J. M. Sánchez: A methodology for reconfigurable hardware design based upon evolutionary computation. Microprocessors and Microsystems 28(7): 363-371 (2004)
2003
18	EE	José Ignacio Hidalgo, Francisco Fernández de Vega, Juan Lanchares, Juan Manuel Sánchez-Pérez, Román Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica: Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. GECCO 2003: 2109-2120
17	EE	Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida: Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. PATMOS 2003: 151-160
16	EE	José Ignacio Hidalgo, Manuel Prieto, Juan Lanchares, Ranieri Baraglia, Francisco Tirado, Oscar Garnica: Hybrid Parallelization of a Compact Genetic Algorithm. PDP 2003: 449-455
2002
15	EE	Juan de Vicente, Juan Lanchares, Román Hermida: FPGA Placement by Thermodynamic Combinatorial Optimization. DATE 2002: 54-60
14	EE	Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida: Optimization of Equational Specifications Using Genetic Techniques. DSD 2002: 252-258
13	EE	José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida: A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. DSD 2002: 60-69
12	EE	Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida: Transformation of Equational Specification by Means of Genetic Programming. EuroGP 2002: 248-257
11	EE	Oscar Garnica, Juan Lanchares, Román Hermida: A New Methodology to Design Low-Power Asynchronous Circuits. PATMOS 2002: 108-117
10		Oscar Garnica, Juan Lanchares, Román Hermida: Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. Fundam. Inform. 50(2): 155-174 (2002)
2001
9	EE	Oscar Garnica, Juan Lanchares, Román Hermida: Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. ACSD 2001: 167-178
8	EE	Oscar Garnica, Juan Lanchares, Román Hermida: A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. DATE 2001: 810
7	EE	Aitor Ibarra, Juan Lanchares, José Ignacio Hidalgo, F. Saenz: Pipelined Genetic Architecture with Fitness on the Fly. DSD 2001: 382-385
2000
6	EE	José Ignacio Hidalgo, Juan Lanchares, Román Hermida: Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms. EUROMICRO 2000: 1204-1211
5	EE	Juan de Vicente, Juan Lanchares, Román Hermida: Adaptive FPGA Placement by Natural Optimization. IEEE International Workshop on Rapid System Prototyping 2000: 188-193
1999
4		Juan de Vicente, Juan Lanchares, Román Hermida: Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. FPL 1999: 91-100
3	EE	José Ignacio Hidalgo, Manuel Prieto, Juan Lanchares, Francisco Tirado, B. de Andrés, S. Esteban, D. Rivera: A Method for Model Parameter Identification Using Parallel Genetic Algorithms. PVM/MPI 1999: 291-298
1998
2	EE	Juan de Vicente, Juan Lanchares, Román Hermida: RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. EUROMICRO 1998: 10192-10195
1997
1	EE	José Ignacio Hidalgo, Juan Lanchares: Functional Partitioning for Hardware-Software Codesign using Genetic Algorithms. EUROMICRO 1997: 631-638

Coauthor Index

1	David H. Albonesi	[28] [29]
2	B. de Andrés	[3]
3	David Atienza	[27] [32] [34]
4	Christos Baloukas	[27]
5	Ranieri Baraglia	[16] [18]
6	Francky Catthoor	[27]
7	José Manuel Colmenar	[21] [22] [23] [24] [25] [26] [33]
8	Steven G. Dropsho (Steve Dropsho)	[28] [29]
9	S. Esteban	[3]
10	Francisco Fernández	[19]
11	Oscar Garnica	[8] [9] [10] [11] [16] [17] [18] [21] [22] [23] [24] [25] [26] [28] [29] [33] [35]
12	Daniel Lombraña Gonzalez	[30] [31]
13	Román Hermida	[2] [4] [5] [6] [8] [9] [10] [11] [12] [13] [14] [15] [17] [18] [20] [21]
14	José Ignacio Hidalgo	[1] [3] [6] [7] [12] [13] [14] [16] [17] [18] [19] [21] [22] [23] [24] [25] [26] [27] [30] [31] [32] [33] [34] [35]
15	Aitor Ibarra	[7] [12] [13] [14]
16	Sonia López	[17] [21] [23] [24] [26] [28] [29]
17	Stylianos Mamagkakis (Stelios Mamagkakis)	[27]
18	Jose Manuel Mendias (José M. Mendías)	[12] [14]
19	Guadalupe Miñana	[22] [23] [24] [25] [26]
20	Noelia Morón	[33]
21	Lazaros Papadopoulos	[27]
22	Raffaele Perego	[18]
23	Christophe Poucet	[27]
24	Manuel Prieto (Manuel Prieto-Matías)	[3] [16]
25	José Luis Risco-Martín (José L. Risco-Martín)	[32] [34] [35]
26	D. Rivera	[3]
27	F. Saenz	[7]
28	J. M. Sánchez	[19]
29	Juan Manuel Sánchez-Pérez	[18]
30	Dimitrios Soudris (D. J. Soudris)	[27]
31	Francisco Tirado	[3] [16]
32	Marco Tomassini	[18]
33	Francisco Fernández de Vega	[18] [30] [31]
34	Juan de Vicente	[2] [4] [5] [15] [20]