| 2009 |
| 43 | EE | Elena Dubrova:
Finding matching initial states for equivalent NLFSRs in the fibonacci and the galois configurations
CoRR abs/0903.3182: (2009) |
| 2008 |
| 42 | EE | Elena Dubrova,
Maxim Teslenko,
Hannu Tenhunen:
On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers.
DATE 2008: 1286-1291 |
| 41 | EE | Elena Dubrova:
Self-Organization for Fault-Tolerance.
IWSOS 2008: 145-156 |
| 40 | EE | Elena Dubrova:
An equivalence preserving transformation from the Fibonacci to the Galois NLFSRs
CoRR abs/0801.4079: (2008) |
| 2007 |
| 39 | EE | Vasilios Lirigis,
Elena Dubrova:
Evaluation and Comparison of Threshold Logic Gates.
ISMVL 2007: 52 |
| 2006 |
| 38 | EE | Elena Dubrova:
Random Multiple-Valued Networks: Theory and Applications.
ISMVL 2006: 27 |
| 2005 |
| 37 | EE | René Krenz,
Elena Dubrova:
A fast algorithm for finding common multiple-vertex dominators in circuit graphs.
ASP-DAC 2005: 529-532 |
| 36 | EE | René Krenz,
Elena Dubrova:
Improved Boolean function hashing based on multiple-vertex dominators.
ASP-DAC 2005: 573-578 |
| 35 | EE | Petra Färm,
Elena Dubrova,
Andreas Kuehlmann:
Logic optimization using rule-based randomized search.
ASP-DAC 2005: 998-1001 |
| 34 | EE | Elena Dubrova:
Structural Testing Based on Minimum Kernels.
DATE 2005: 1168-1173 |
| 33 | EE | Maxim Teslenko,
Elena Dubrova:
An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs.
DATE 2005: 406-411 |
| 32 | EE | Andrés Martinelli,
Elena Dubrova:
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition.
DATE 2005: 430-431 |
| 31 | | Elena Dubrova,
Maxim Teslenko,
Hannu Tenhunen:
Computing attractors in dynamic networks.
IADIS AC 2005: 535-542 |
| 30 | | Elena Dubrova,
Maxim Teslenko,
Andrés Martinelli:
Kauffman networks: analysis and applications.
ICCAD 2005: 479-484 |
| 29 | EE | Elena Dubrova:
Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs.
ISCAS (3) 2005: 2212-2215 |
| 28 | EE | Maxim Teslenko,
Andrés Martinelli,
Elena Dubrova:
Bound-Set Preserving ROBDD Variable Orderings May Not Be Optimum.
IEEE Trans. Computers 54(2): 236-237 (2005) |
| 2004 |
| 27 | EE | Andrés Martinelli,
René Krenz,
Elena Dubrova:
Disjoint-support Boolean decomposition combining functional and structural methods.
ASP-DAC 2004: 597-599 |
| 26 | EE | Maxim Teslenko,
Elena Dubrova:
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth.
ICCAD 2004: 748-751 |
| 25 | | Elena Dubrova,
Maxim Teslenko,
Andrés Martinelli:
On relation between non-disjoint decomposition and multiple-vertex dominators.
ISCAS (4) 2004: 493-496 |
| 24 | EE | Elena Dubrova:
A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions.
ISMVL 2004: 309-314 |
| 2003 |
| 23 | EE | Elena Dubrova,
Maxim Teslenko,
Johan Karlsson:
Boolean Decomposition Based on Cyclic Chains.
ICCD 2003: 504-509 |
| 22 | EE | René Krenz,
Elena Dubrova,
Andreas Kuehlmann:
Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation.
ISMVL 2003: 334- |
| 21 | EE | Elena Dubrova:
Implementation of Multiple-Valued Functions Using Literal-Splitting Technique.
ISMVL 2003: 7-10 |
| 2002 |
| 20 | EE | Elena Dubrova:
Composition Trees in Finding Best Variable Orderings for ROBDDs.
DATE 2002: 1084 |
| 19 | EE | Jimson Mathew,
Elena Dubrova:
Self-Checking 1-out-of-n CMOS Current-Mode Checker.
DFT 2002: 69-77 |
| 18 | EE | Elena Dubrova,
Petra Färm:
A Conjunctive Canonical Expansion of Multiple-Valued Functions.
ISMVL 2002: 35-38 |
| 17 | | Petra Färm,
Elena Dubrova:
Technology Mapping for Chemically Assembled Electronic Nanotechnology.
IWLS 2002: 121-124 |
| 16 | | René Krenz,
Elena Dubrova,
Andreas Kuehlmann:
Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions.
IWLS 2002: 321-326 |
| 15 | | Tomas Bengtsson,
Andrés Martinelli,
Elena Dubrova:
A Fast Heuristic Algorithm for Disjunctive.
IWLS 2002: 51-56 |
| 2001 |
| 14 | | Imed Ben Dhaou,
Elena Dubrova,
Hannu Tenhunen:
Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology.
ISMVL 2001: 61-66 |
| 13 | EE | Hannu Tenhunen,
Elena Dubrova:
SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH.
MSE 2001: 64-66 |
| 2000 |
| 12 | EE | Elena Dubrova,
Peeter Ellervee,
D. Michael Miller,
Jon C. Muzio:
TOP: An Algorithm for Three-Level Optimization of PLDs.
DATE 2000: 751 |
| 11 | EE | Harald Sack,
Elena Dubrova,
Christoph Meinel:
Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions.
ISMVL 2000: 233-238 |
| 10 | EE | Elena Dubrova,
Harald Sack:
Probabilistic Verification of Multiple-Valued Functions.
ISMVL 2000: 460-466 |
| 9 | EE | Elena Dubrova,
Jon C. Muzio:
Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits.
IEEE Trans. Computers 49(11): 1285-1289 (2000) |
| 8 | EE | Elena Dubrova,
Luca Macchiarulo:
A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'.
IEEE Trans. Computers 49(11): 1290-1292 (2000) |
| 1999 |
| 7 | EE | Elena Dubrova:
Evaluation of m-Valued Fixed Polarity Generalizations of Reed-Muller Canonical Form.
ISMVL 1999: 92-98 |
| 6 | | Elena Dubrova,
Harald Sack:
Probabilistic Verification of Multiple-Valued Functions
Universität Trier, Mathematik/Informatik, Forschungsbericht 99-23: (1999) |
| 5 | | Harald Sack,
Elena Dubrova,
Christoph Meinel:
Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions.
Universität Trier, Mathematik/Informatik, Forschungsbericht 99-27: (1999) |
| 1997 |
| 4 | EE | Elena Dubrova,
Jon C. Muzio,
Bernhard von Stengel:
Finding Composition Trees for Multiple-Valued Functions.
ISMVL 1997: 19-26 |
| 1996 |
| 3 | EE | Elena Dubrova,
Jon C. Muzio:
Testability of Generalized Multiple-Valued Reed-Muller Circuits.
ISMVL 1996: 56-61 |
| 1995 |
| 2 | EE | Elena Dubrova,
Dilian Gurov,
Jon C. Muzio:
The Evaluation of Full Sensitivity for Test Generation in MVL Circuits.
ISMVL 1995: 104- |
| 1994 |
| 1 | | Elena Dubrova,
Dilian Gurov,
Jon C. Muzio:
Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits.
ISMVL 1994: 284-288 |