Bruno Rouzeyre

2008
33	EE	M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre: AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. DELTA 2008: 314-321
32	EE	Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: An Integrated Validation Environment for Differential Power Analysis. DELTA 2008: 527-532
31	EE	Julien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre: Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI 2008: 139-144
2007
30		Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: A Novel Parity Bit Scheme for SBox in AES Circuits. DDECS 2007: 267-271
29	EE	Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS 2007: 57-62
28		Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: A Dependable Parallel Architecture for SBoxes. ReCoSoC 2007: 132-137
27	EE	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Test data compression and TAM design. VLSI-SoC 2007: 178-183
26	EE	Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre: Mutation Sampling Technique for the Generation of Structural Test Data CoRR abs/0710.4802: (2007)
25	EE	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Securing Scan Control in Crypto Chips. J. Electronic Testing 23(5): 457-464 (2007)
2006
24	EE	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: A secure scan design methodology. DATE 2006: 1177-1178
23	EE	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA 2006: 295-300
22	EE	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Secure Scan Techniques: A Comparison. IOLTS 2006: 119-124
2005
21	EE	Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre: Mutation Sampling Technique for the Generation of Structural Test Data. DATE 2005: 1022-1023
2004
20	EE	Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre: An Arithmetic Structure for Test Data Horizontal Compression. DATE 2004: 428-435
19	EE	Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre: On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA 2004: 275-280
18	EE	David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell: Scan Design and Secure Chip. IOLTS 2004: 219-226
17		Solaiman Rahim, Bruno Rouzeyre, Lionel Torres: A Flip-Flop Matching Engine to Verify Sequential Optimizations. Computers and Artificial Intelligence 23(5): (2004)
2002
16		Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes: SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France Kluwer 2002
15	EE	Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre: A Heuristic for Test Scheduling at System Level. DATE 2002: 1124
14	EE	Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-291
2001
13		Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre: Functional Test Generation using Constraint Logic Programming. VLSI-SOC 2001: 375-387
12		Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre: Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. VLSI-SOC 2001: 401-412
11	EE	David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis. J. Electronic Testing 17(3-4): 331-339 (2001)
2000
10		David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: BISTing data paths at behavioral level. ITC 2000: 672-680
1999
9	EE	David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: BISTing Datapaths under Heterogeneous Test Schemes. J. Electronic Testing 14(1-2): 115-123 (1999)
1998
8	EE	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre: Alleviating DFT Cost Using Testability Driven HLS. Asian Test Symposium 1998: 46-51
7	EE	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. DATE 1998: 921-922
6	EE	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Low Cost Partial Scan Design: A High Level Synthesis Approach. VTS 1998: 332-340
1997
5	EE	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre: Analyzing testability from behavioral to RT level. ED&TC 1997: 158-165
4	EE	Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre: Improving Testability of Non-Scan Designs during Behavioral Synthesis. J. Electronic Testing 11(1): 29-42 (1997)
1995
3		Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre: Is High-Level Test Synthesis Just Design for Test? ITC 1995: 294
1994
2		Bruno Rouzeyre, D. Dupont, G. Sagnes: Component Selection, Scheduling and Control Schemes for High Level Synthesis. EDAC-ETC-EUROASIC 1994: 482-489
1		Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre: Automatic Synthesis of BISTed Data Paths From High Level Specification. EDAC-ETC-EUROASIC 1994: 591-598

Coauthor Index

1	Frédéric Bancel	[18] [22] [24] [25]
2	Nicolas Bérard	[18]
3	Vincent Beroulle	[21] [26]
4	David Berthelot	[9] [10] [11]
5	Maciej J. Ciesielski	[13] [14]
6	Érika F. Cota	[31]
7	Julien Dalmasso	[23] [27] [31]
8	M. Doulcier	[33]
9	D. Dupont	[2]
10	Marie-Lise Flottes	[1] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [15] [16] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33]
11	D. Hammad	[1] [4]
12	David Hély	[18] [22] [24] [25]
13	Priyank Kalla	[14]
14	Christian Landrault	[3]
15	Giorgio Di Natale	[28] [29] [30] [32]
16	Christian Piguet	[16]
17	R. Pires	[5] [6] [7] [8]
18	Regis Poirier	[19] [20]
19	Julien Pouget	[12] [15]
20	Solaiman Rahim	[17]
21	Michel Renovell	[18]
22	Chantal Robach	[21] [26]
23	Michel Robert	[16]
24	G. Sagnes	[2]
25	Mathieu Scholivé	[21] [26]
26	Lionel Torres	[17]
27	L. Volpe	[6] [7]
28	Zhihong Zeng	[13] [14]

Colors in the list of coauthors