| 2008 |
|---|
| 12 | EE | Hsin-Hsiung Huang,
Hui-Yu Huang,
Yu-Cheng Lin,
Tsai-Ming Hsieh:
Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system.
ISCAS 2008: 1200-1203 |
| 11 | EE | Hsin-Hsiung Huang,
Shu-Ping Chang,
Yu-Cheng Lin,
Tsai-Ming Hsieh:
Timing-driven X-architecture router among rectangular obstacles.
ISCAS 2008: 1804-1807 |
| 2006 |
|---|
| 10 | EE | Hsin-Hsiung Huang,
Yung-Ching Chen,
Tsai-Ming Hsieh:
A congestion-driven buffer planner with space reservation.
ISCAS 2006 |
| 2005 |
|---|
| 9 | EE | Chin-Hui Wang,
Yung-Ching Chen,
Tsai-Ming Hsieh,
Chih-Hung Lee,
Hsin-Hsiung Huang:
A new congestion and crosstalk aware router.
ISCAS (6) 2005: 6234-6237 |
| 8 | EE | Chih-Hung Lee,
Chin-Hung Su,
Shih-Hsu Huang,
Chih-Yuan Lin,
Tsai-Ming Hsieh:
Floorplanning with clock tree estimation.
ISCAS (6) 2005: 6244-6247 |
| 2004 |
|---|
| 7 | EE | Yi-Lin Hsieh,
Tsai-Ming Hsieh:
A New Effective Congestion Model in Floorplan Design.
DATE 2004: 1204-1209 |
| 2002 |
|---|
| 6 | EE | Chih-Hung Lee,
Wen-Yu Fu,
Chung-Chiao Chang,
Tsai-Ming Hsieh:
An efficient hierarchical approach for general floorplan area minimization.
APCCAS (2) 2002: 347-352 |
| 5 | EE | Chih-Hung Lee,
Yu-Chung Lin,
Wen-Yu Fu,
Chung-Chiao Chang,
Tsai-Ming Hsieh:
A New Formulation for SOC Floorplan Area Minimization Problem.
DATE 2002: 1100 |
| 4 | EE | Chih-Hung Lee,
Yi-Lin Hsieh,
Hui-Chun Lee,
Tsai-Ming Hsieh:
Sequence-pair based placement with boundary constraints.
ISCAS (1) 2002: 341-344 |
| 3 | EE | Chih-Hung Lee,
Yu-Chung Lin,
Hsin-Hsiung Huang,
Tsai-Ming Hsieh:
Structural Decomposition with Functional Considerations for Low Power.
ISQED 2002: 464-469 |
| 2001 |
|---|
| 2 | EE | Po-Xun Chiu,
Yu-Chung Lin,
Yi-Ling Hsieh,
Tsai-Ming Hsieh:
Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint.
ISCAS (5) 2001: 519-522 |
| 2000 |
|---|
| 1 | EE | Yu-Chung Lin,
Su-Feng Tseng,
Tsai-Ming Hsieh:
Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract).
FPGA 2000: 217 |
