2007 | ||
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20 | EE | Paolo Azzoni, Massimo Bertoletti, Nicola Dragone, Franco Fummi, Carlo Guardiani, W. Vendraminetto: Yield-aware placement optimization. DATE 2007: 1232-1237 |
19 | EE | Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki: DFM/DFY: should you trust the surgeon or the family doctor? DATE 2007: 439-442 |
2005 | ||
18 | EE | Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan: DFM rules! DAC 2005: 168-169 |
17 | EE | Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, Patrick McNamara: An effective DFM strategy requires accurate process and IP pre-characterization. DAC 2005: 760-761 |
2004 | ||
16 | EE | Franco Bagnoli, Carlo Guardiani: Sympatric Speciation Through Assortative Mating in a Long-Range Cellular Automaton. ACRI 2004: 405-414 |
15 | EE | Nicola Dragone, Michele Quarantelli, Massimo Bertoletti, Carlo Guardiani: High Yield Standard Cell Libraries: Optimization and Modeling. PATMOS 2004: 129-137 |
2002 | ||
14 | EE | Carlo Guardiani, Patrick McNamara, Lidia Daldoss, Sharad Saxena, Stefano Zanella, Wei Xiang, Suli Liu: Analog IP Testing: Diagnosis and Optimization. DATE 2002: 192-196 |
13 | EE | Enrico Malavasi, Stefano Zanella, Min Cao, Julian Uschersohn, Mike Misheloff, Carlo Guardiani: Impact Analysis of Process Variability on Clock Skew. ISQED 2002: 129-132 |
2001 | ||
12 | EE | Stefano Zanella, Andrea Neviani, Enrico Zanoni, Paolo Miliozzi, Edoardo Charbon, Carlo Guardiani, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli: Modeling of Substrate Noise Injected by Digital Libraries. ISQED 2001: 488- |
2000 | ||
11 | EE | Carlo Guardiani, Sharad Saxena, Patrick McNamara, Phillip Schumaker, Dale Coder: An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects. DAC 2000: 15-18 |
10 | EE | Carlo Guardiani, Andrzej J. Strojwas: Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? ISQED 2000: 447- |
9 | EE | Alessandra Nardi, Andrea Neviani, Carlo Guardiani: Realistic Worst-Case Modeling by Performance Level Principal Component Analysis. ISQED 2000: 455-460 |
1999 | ||
8 | EE | Mauro Chinosi, Roberto Zafalon, Carlo Guardiani: Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning. DAC 1999: 562-567 |
1998 | ||
7 | Davide Pandini, Primo Scandolara, Carlo Guardiani: Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs. ASP-DAC 1998: 45-50 | |
6 | EE | Mauro Chinosi, Roberto Zafalon, Carlo Guardiani: Automatic characterization and modeling of power consumption in static RAMs. ISLPED 1998: 112-114 |
5 | EE | Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano: Power invariant vector compaction based on bit clustering and temporal partitioning. ISLPED 1998: 118-120 |
1997 | ||
4 | EE | Cristiano Forzan, Bruno Franzini, Carlo Guardiani: Accurate and Efficient Macromodel of Submicron Digital Standard Cells. DAC 1997: 633-637 |
1996 | ||
3 | EE | Eric Felt, Stefano Zanella, Carlo Guardiani, Alberto L. Sangiovanni-Vincentelli: Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling. ICCAD 1996: 374-380 |
2 | EE | Andrzej J. Strojwas, Michele Quarantelli, J. Borel, Carlo Guardiani, G. Nicollini, G. Crisenza, Bruno Franzini, J. Wiart: Manufacturability of low power CMOS technology solutions. ISLPED 1996: 225-232 |
1995 | ||
1 | EE | Alessandro Dal Fabbro, Bruno Franzini, Luigi Croce, Carlo Guardiani: An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells. DAC 1995: 702-706 |