| 2009 |
|---|
| 63 | EE | Yu-Min Kuo,
Yue-Lung Chang,
Shih-Chieh Chang:
Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 417-425 (2009) |
| 62 | EE | Yu-Min Kuo,
Ya-Ting Chang,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Spare Cells With Constant Insertion for Engineering Change.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 456-460 (2009) |
| 2008 |
|---|
| 61 | EE | Cheng-Tao Hsieh,
Jason Cong,
Zhiru Zhang,
Shih-Chieh Chang:
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.
ASP-DAC 2008: 10-15 |
| 60 | EE | Yu-Min Kuo,
Shih-Hung Weng,
Shih-Chieh Chang:
A novel sequential circuit optimization with clock gating logic.
ICCAD 2008: 230-233 |
| 59 | EE | Shih-Hung Weng,
Yu-Min Kuo,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Timing analysis considering IR drop waveforms in power gating designs.
ICCD 2008: 532-537 |
| 58 | EE | Yu-Shih Su,
Po-Hsien Chang,
Shih-Chieh Chang,
TingTing Hwang:
Synthesis of a novel timing-error detection architecture.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 2007 |
|---|
| 57 | EE | Cheng-Hung Lin,
Yu-Tang Tai,
Shih-Chieh Chang:
Optimization of pattern matching algorithm for memory based architecture.
ANCS 2007: 11-16 |
| 56 | EE | De-Shiuan Chiou,
Da-Cheng Juan,
Yu-Ting Chen,
Shih-Chieh Chang:
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization.
DAC 2007: 81-86 |
| 55 | EE | Yu-Shih Su,
Da-Chung Wang,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs.
DAC 2007: 976-981 |
| 54 | EE | Yu-Min Kuo,
Ya-Ting Chang,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Engineering change using spare cells with constant insertion.
ICCAD 2007: 544-547 |
| 53 | EE | Yu-Ting Chen,
Da-Cheng Juan,
Ming-Chao Lee,
Shih-Chieh Chang:
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon.
ICCAD 2007: 779-782 |
| 52 | EE | Aida Todri,
Malgorzata Marek-Sadowska,
Shih-Chieh Chang:
Analysis and optimization of power-gated ICs with multiple power gating configurations.
ICCAD 2007: 783-790 |
| 51 | EE | Aida Todri,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Electromigration and voltage drop aware power grid optimization for power gated ICs.
ISLPED 2007: 391-394 |
| 50 | EE | Yu-Min Kuo,
Cheng-Hung Lin,
Chun-Yao Wang,
Shih-Chieh Chang,
Pei-Hsin Ho:
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure.
ISQED 2007: 344-349 |
| 49 | EE | Cheng-Tao Hsieh,
Jian-Cheng Lin,
Shih-Chieh Chang:
Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis.
ISQED 2007: 602-606 |
| 48 | EE | Cheng-Hung Lin,
Chih-Tsun Huang,
Chang-Ping Jiang,
Shih-Chieh Chang:
Optimization of Pattern Matching Circuits for Regular Expression on FPGA.
IEEE Trans. VLSI Syst. 15(12): 1303-1310 (2007) |
| 2006 |
|---|
| 47 | EE | Kai-Chiang Wu,
Cheng-Tao Hsieh,
Shih-Chieh Chang:
Delay variation tolerance for domino circuits.
ASP-DAC 2006: 354-359 |
| 46 | EE | De-Shiuan Chiou,
Shih-Hsin Chen,
Shih-Chieh Chang,
Chingwei Yeh:
Timing driven power gating.
DAC 2006: 121-124 |
| 45 | EE | Cheng-Hung Lin,
Chih-Tsun Huang,
Chang-Ping Jiang,
Shih-Chieh Chang:
Optimization of regular expression pattern matching circuits on FPGA.
DATE Designers' Forum 2006: 12-17 |
| 44 | EE | Yu-Min Kuo,
Yue-Lung Chang,
Shih-Chieh Chang:
Efficient Boolean characteristic function for fast timed ATPG.
ICCAD 2006: 96-99 |
| 43 | EE | Yi-Le Huang,
Chun-Yao Wang,
Richard Yeh,
Shih-Chieh Chang,
Yung-Chih Chen:
Language-Based High Level Transaction Extraction on On-chip Buses.
ISQED 2006: 231-236 |
| 42 | EE | Zhong-Zhen Wu,
Shih-Chieh Chang:
Multiple wire reconnections based on implication flow graph.
ACM Trans. Design Autom. Electr. Syst. 11(4): 939-952 (2006) |
| 41 | EE | Tzyy-Kuen Tien,
Chih-Shen Tsai,
Shih-Chieh Chang,
Chingwei Yeh:
Power minimization for dynamic PLAs.
IEEE Trans. VLSI Syst. 14(6): 616-624 (2006) |
| 2005 |
|---|
| 40 | EE | Cheng-Hung Lin,
Yung-Chang Huang,
Shih-Chieh Chang,
Wen-Ben Jone:
Design and design automation of rectification logic for engineering change.
ASP-DAC 2005: 1006-1009 |
| 39 | EE | Tzyy-Kuen Tien,
Chih-Shen Tsai,
Shih-Chieh Chang,
Chingwei Yeh:
Power minimization for dynamic PLAs.
ASP-DAC 2005: 1010-1013 |
| 38 | EE | Yen-Fong Lee,
Shi-Yu Huang,
Sheng-Yu Hsu,
I-Ling Chen,
Cheng-Tao Shieh,
Jian-Cheng Lin,
Shih-Chieh Chang:
Power estimation starategies for a low-power security processor.
ASP-DAC 2005: 367-371 |
| 37 | EE | Wai-Chung Tang,
Wing-Hang Lo,
Yu-Liang Wu,
Shih-Chieh Chang:
FPGA technology mapping optimization by rewiring algorithms.
ISCAS (6) 2005: 5653-5656 |
| 2004 |
|---|
| 36 | EE | S. Ghosh,
K. W. Lai,
Wen-Ben Jone,
Shih-Chieh Chang:
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.
Asian Test Symposium 2004: 210-215 |
| 35 | EE | Shih-Chieh Chang,
Cheng-Tao Hsieh,
Kai-Chiang Wu:
Re-synthesis for delay variation tolerance.
DAC 2004: 814-819 |
| 34 | EE | Cheng-Tao Hsieh,
Jian-Cheng Lin,
Shih-Chieh Chang:
A vectorless estimation of maximum instantaneous current for sequential circuits.
ICCAD 2004: 537-540 |
| 2003 |
|---|
| 33 | EE | J. H. Jiang,
Wen-Ben Jone,
Shih-Chieh Chang,
S. Ghosh:
Embedded core test generation using broadcast test architecture and netlist scrambling.
IEEE Transactions on Reliability 52(4): 435-443 (2003) |
| 2002 |
|---|
| 32 | EE | Tzyy-Kuen Tien,
Tong-Kai Tsai,
Shih-Chieh Chang:
Crosstalk Alleviation for Dynamic PLAs.
DATE 2002: 683-689 |
| 31 | EE | Jiann-Chyi Rau,
Y. M. Chen,
Shih-Chieh Chang:
A don't-care based image circuit for function verification.
ISCAS (5) 2002: 325-328 |
| 30 | EE | Tzyy-Kuen Tien,
Shih-Chieh Chang,
Tong-Kai Tsai:
Crosstalk alleviation for dynamic PLAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1416-1424 (2002) |
| 2001 |
|---|
| 29 | EE | J. H. Jiang,
Shih-Chieh Chang,
Wen-Ben Jone:
Embedded Core Testing Using Broadcast Test Architecture.
DFT 2001: 95-103 |
| 28 | EE | Shih-Chieh Chang,
Jiann-Chyi Rau:
A timing-driven pseudoexhaustive testing for VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 147-158 (2001) |
| 27 | EE | Shih-Chieh Chang,
Ching-Hwa Cheng,
Wen-Ben Jone,
Shin-De Lee,
Jinn-Shyan Wang:
Charge-sharing alleviation and detection for CMOS domino circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 266-280 (2001) |
| 26 | EE | Shih-Chieh Chang,
Zhong-Zhen Wu:
Theorems and extensions of single wire replacement.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1159-1164 (2001) |
| 2000 |
|---|
| 25 | EE | Yin-He Su,
Ching-Hwa Cheng,
Shih-Chieh Chang:
Novel techniques for improving testability analysis.
Asian Test Symposium 2000: 392-397 |
| 24 | EE | Ching-Hwa Cheng,
Wen-Ben Jone,
Jinn-Shyan Wang,
Shih-Chieh Chang:
Charge sharing fault analysis and testing for CMOS domino logic circuits.
Asian Test Symposium 2000: 435-440 |
| 23 | EE | Ching-Hwa Cheng,
Jinn-Shyan Wang,
Shih-Chieh Chang,
Wen-Ben Jone:
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.
DFT 2000: 329-337 |
| 22 | | Ching-Hwa Cheng,
Shih-Chieh Chang,
Shin-De Li,
Wen-Ben Jone,
Jinn-Shyan Wang:
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.
ICCAD 2000: 387-390 |
| 21 | | Shih-Chieh Chang,
Zhong-Zhen Wu,
He-Zhe Yu:
Wire Reconnections Based on Implication Flow Graph.
ICCAD 2000: 533-536 |
| 20 | EE | Shih-Chieh Chang,
Wen-Ben Jone,
Shi-Sen Chang:
TAIR: testability analysis by implication reasoning.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 152-160 (2000) |
| 1999 |
|---|
| 19 | EE | Ching-Wei Yeh,
Min-Cheng Chang,
Shih-Chieh Chang,
Wen-Ben Jone:
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications.
DAC 1999: 68-71 |
| 18 | EE | Ching-Hwa Cheng,
Shih-Chieh Chang,
Jinn-Shyan Wang,
Wen-Ben Jone:
Charge Sharing Fault Detection for CMOS Domino Logic Circuits.
DFT 1999: 77-85 |
| 17 | EE | Shih-Chieh Chang,
Jung-Cheng Chuang,
Zhong-Zhen Wu:
Synthesis for multiple input wires replacement of a gate for wiring consideration.
ICCAD 1999: 115-119 |
| 16 | EE | Chingwei Yeh,
Min-Cheng Chang,
Shih-Chieh Chang,
Wen-Ben Jone:
Power reduction through iterative gate sizing and voltage scaling.
ISCAS (1) 1999: 246-249 |
| 15 | | Shih-Chieh Chang,
Lukas P. P. P. van Ginneken,
Malgorzata Marek-Sadowska:
Circuit Optimization by Rewiring.
IEEE Trans. Computers 48(9): 962-970 (1999) |
| 14 | EE | Shih-Chieh Chang,
David Ihsin Cheng:
Efficient Boolean division and substitution using redundancy addition and removing.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1096-1106 (1999) |
| 1998 |
|---|
| 13 | EE | Shih-Chieh Chang,
David Ihsin Cheng:
Efficient Boolean Division and Substitution.
DAC 1998: 342-347 |
| 12 | EE | Wen-Ben Jone,
Jiann-Chyi Rau,
Shih-Chieh Chang,
Yu-Liang Wu:
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.
ITC 1998: 322-330 |
| 11 | EE | Shih-Chieh Chang,
Shi-Sen Chang,
Wen-Ben Jone,
Chien-Chung Tsai:
A novel combinational testability analysis by considering signal correlation.
ITC 1998: 658-667 |
| 1997 |
|---|
| 10 | EE | Shih-Chieh Chang,
Kwang-Ting Cheng,
Nam Sung Woo,
Malgorzata Marek-Sadowska:
Postlayout logic restructuring using alternative wires.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 587-596 (1997) |
| 1996 |
|---|
| 9 | EE | Shih-Chieh Chang,
Lukas P. P. P. van Ginneken,
Malgorzata Marek-Sadowska:
Fast Boolean optimization by rewiring.
ICCAD 1996: 262-269 |
| 8 | EE | Shih-Chieh Chang,
Malgorzata Marek-Sadowska,
TingTing Hwang:
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1226-1236 (1996) |
| 7 | EE | Shih-Chieh Chang,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng:
Perturb and simplify: multilevel Boolean network optimizer.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1494-1504 (1996) |
| 1995 |
|---|
| 6 | EE | Chih-Chang Lin,
Kuang-Chien Chen,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng:
Logic Synthesis for Engineering Change.
DAC 1995: 647-652 |
| 5 | EE | Shih-Chieh Chang,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng:
An Efficient Algorithm for Local Don't Care Sets Calculation.
DAC 1995: 663-667 |
| 1994 |
|---|
| 4 | EE | Shih-Chieh Chang,
Kwang-Ting Cheng,
Nam Sung Woo,
Malgorzata Marek-Sadowska:
Layout Driven Logic Synthesis for FPGAs.
DAC 1994: 308-313 |
| 3 | | Shih-Chieh Chang,
David Ihsin Cheng,
Malgorzata Marek-Sadowska:
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions.
EDAC-ETC-EUROASIC 1994: 620-624 |
| 2 | EE | Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Perturb and simplify: multi-level boolean network optimizer.
ICCAD 1994: 2-5 |
| 1992 |
|---|
| 1 | | Shih-Chieh Chang,
Malgorzata Marek-Sadowska:
Technology Mapping via Transformations of Function Graphs.
ICCD 1992: 159-162 |
