2008 |
10 | EE | Julien Francq,
Jean-Baptiste Rigaud,
Pascal Manet,
Assia Tria,
Arnaud Tisserand:
Error Detection for Borrow-Save Adders Dedicated to ECC Unit.
FDTC 2008: 77-86 |
2007 |
9 | EE | Régis Leveugle,
Abdelaziz Ammari,
V. Maingot,
E. Teyssou,
Pascal Moitrel,
Christophe Mourtel,
Nathalie Feyt,
Jean-Baptiste Rigaud,
Assia Tria:
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling.
DATE 2007: 1587-1592 |
8 | EE | Reouven Elbaz,
Lionel Torres,
Gilles Sassatelli,
Pierre Guillemin,
C. Anguille,
Michel Bardouillet,
Christian Buatois,
Jean-Baptiste Rigaud:
Hardware Engines for Bus Encryption: A Survey of Existing Techniques
CoRR abs/0710.4803: (2007) |
2006 |
7 | | Pascal Manet,
Jean-Baptiste Rigaud,
Julien Francq,
Marc Jeambrun,
Assia Tria,
Bruno Robisson,
Jerome Quartana,
Selma Laabidi:
Integrated Evaluation Platform for Secured Devices.
ReCoSoC 2006: 214-219 |
2005 |
6 | EE | Reouven Elbaz,
Lionel Torres,
Gilles Sassatelli,
Pierre Guillemin,
C. Anguille,
Michel Bardouillet,
Christian Buatois,
Jean-Baptiste Rigaud:
Hardware Engines for Bus Encryption: A Survey of Existing Techniques.
DATE 2005: 40-45 |
2003 |
5 | EE | Dominique Borrione,
Menouer Boubekeur,
Emil Dumitrescu,
Marc Renaudin,
Jean-Baptiste Rigaud,
Antoine Sirianni:
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow.
HICSS 2003: 279 |
4 | EE | Philippe Maurine,
Jean-Baptiste Rigaud,
G. Fraidy Bouesse,
Gilles Sicard,
Marc Renaudin:
Statistic Implementation of QDI Asynchronous Primitives.
PATMOS 2003: 181-191 |
2002 |
3 | EE | Jean-Baptiste Rigaud,
Laurent Fesquet,
Marc Renaudin,
Jerome Quartana:
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems.
DATE 2002: 1090 |
2 | EE | Quoc Thai Ho,
Jean-Baptiste Rigaud,
Laurent Fesquet,
Marc Renaudin,
Robin Rolland:
Implementing Asynchronous Circuits on LUT Based FPGAs.
FPL 2002: 36-46 |
2001 |
1 | | Jean-Baptiste Rigaud,
Jerome Quartana,
Laurent Fesquet,
Marc Renaudin:
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.
VLSI-SOC 2001: 313-324 |