Luis Entrena

Luis Entrena-Arrontes

2009
36	EE	Mario García-Valderas, Luis Entrena, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García: SET Emulation Under a Quantized Delay Model. J. Electronic Testing 25(1): 107-116 (2009)
2008
35	EE	Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez: Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. FPL 2008: 539-542
2007
34	EE	Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez: Wavelet-Based Fingerprint Region Selection. CAIP 2007: 391-398
33	EE	Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena: SET Emulation Under a Quantized Delay Model. DFT 2007: 68-77
32	EE	Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán: Correlation-Based Fingerprint Matching with Orientation Field Alignment. ICB 2007: 713-721
31	EE	Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena: A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. IOLTS 2007: 101-106
30	EE	Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Techniques for Fast Transient Fault Grading Based on Autonomous Emulation CoRR abs/0710.4757: (2007)
29	EE	Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena: Low power data processing system with self-reconfigurable architecture. Journal of Systems Architecture 53(9): 568-576 (2007)
2006
28		Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes: An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. DDECS 2006: 218-219
27	EE	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena: Fault Injection-based Reliability Evaluation of SoPCs. European Test Symposium 2006: 75-82
26	EE	Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena: Emulation-based Fault Injection in Circuits with Embedded Memories. IOLTS 2006: 183-184
2005
25	EE	Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. DATE 2005: 308-309
24		Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. FPL 2005: 397-402
23		Almudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez: Correlation-Based Fingerprint Matching Using FPGAs. FPT 2005: 87-94
22	EE	Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. IOLTS 2005: 43-48
2004
21	EE	Raul Sánchez-Reillo, Judith Liu-Jimenez, Luis Entrena: Architectures for Biometric Match-on-Token Solutions. ECCV Workshop BioAW 2004: 195-204
20	EE	Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena: FPGA Implementation of Biometric Authentication System Based on Hand Geometry. FPL 2004: 43-53
19	EE	Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena: Power Consumption Reduction Through Dynamic Reconfiguration. FPL 2004: 751-760
18	EE	Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena: Transient Fault Emulation of Hardened Circuits in FPGA Platforms. IOLTS 2004: 109-114
2003
17	EE	Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo: Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. FPL 2003: 220-229
16	EE	Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo: State Encoding for Low-Power FSMs in FPGA. PATMOS 2003: 31-40
15	EE	Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López: Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. Journal of Systems Architecture 49(12-15): 529-541 (2003)
2002
14	EE	Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López: New Techniques for Speeding-Up Fault-Injection Campaigns. DATE 2002: 847-853
13	EE	Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero: Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. IOLTW 2002: 193
12	EE	Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López: An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. VTS 2002: 229-236
2001
11	EE	José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Functional extension of structural logic optimization techniques. ASP-DAC 2001: 467-472
10	EE	José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE 2001: 391-397
9	EE	Enrique San Millán, Luis Entrena, José Alberto Espejo: On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD 2001: 292-299
8	EE	Enrique San Millán, Luis Entrena, José Alberto Espejo: On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD 2001: 91-94
7	EE	Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo: Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW 2001: 43-47
6	EE	Luis Entrena, Celia López, Emilio Olías: Automatic Insertion of Fault-Tolerant Structures at the RT Level. IOLTW 2001: 48-50
1999
5	EE	Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno: Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE 1999: 516-520
4	EE	José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Logic Restructuring for MUX-Based FPGAs. EUROMICRO 1999: 1161-
1995
3	EE	Serafín Olcoz, Luis Entrena, Luis Berrojo: An effective system development environment based on VHDL prototyping. EURO-DAC 1995: 502-507
2	EE	Luis Entrena-Arrontes, Kwang-Ting Cheng: Combinational and sequential logic optimization by redundancy addition and removal. IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 909-916 (1995)
1993
1	EE	Luis Entrena, Kwang-Ting Cheng: Sequential logic optimization by redundancy addition and removal. ICCAD 1993: 310-315

Coauthor Index

1	Luis Berrojo	[3] [12] [13] [14]
2	Raúl Fernández Cardenal	[33] [36]
3	Fernando Casado	[20]
4	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[1] [2]
5	Silvia Chiusano	[5]
6	Fulvio Corno	[5] [12] [13] [14]
7	José Alberto Espejo	[4] [5] [7] [8] [9] [10] [11] [15]
8	Mario García-Valderas	[18] [19] [22] [24] [25] [26] [28] [30] [31] [33] [36]
9	Isabel González	[12] [13] [14]
10	Juan Izquierdo	[35]
11	Almudena Lindoso	[23] [32] [34] [35]
12	Judith Liu-Jimenez	[20] [21] [23] [32] [34] [35]
13	Celia López-Ongil (Celia López)	[6] [7] [12] [13] [14] [15] [18] [20] [22] [23] [24] [25] [26] [27] [28] [30] [31] [33] [36]
14	Michael G. Lorenz	[16] [17] [19] [29]
15	Luis Mengibar	[16] [17] [19] [29]
16	Enrique San Millán	[4] [5] [7] [8] [9] [10] [11] [15] [29] [32]
17	Serafín Olcoz	[3]
18	Emilio Olías	[4] [6] [7] [10] [11]
19	Marta Portela-García	[18] [22] [24] [25] [26] [27] [28] [30] [31] [33] [36]
20	Matteo Sonza Reorda	[12] [13] [14] [27]
21	Leslie Sánchez	[20]
22	Raul Sánchez-Reillo	[16] [17] [20] [21]
23	Giovanni Squillero	[12] [13] [14]
24	Luca Sterpone	[27]
25	Massimo Violante	[27]

Colors in the list of coauthors