| 2009 |
|---|
| 172 | EE | Frank Hannig,
Hritam Dutta,
Jürgen Teich:
Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.
ARCS 2009: 16-27 |
| 171 | EE | Hritam Dutta,
Frank Hannig,
Jürgen Teich:
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.
ARCS 2009: 233-245 |
| 170 | EE | Dirk Koch,
Christian Beckhoff,
Jürgen Teich:
A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs.
FPGA 2009: 253-256 |
| 169 | EE | Joachim Keinert,
Martin Streubühr,
Thomas Schlichter,
Joachim Falk,
Jens Gladigau,
Christian Haubelt,
Jürgen Teich,
Michael Meredith:
SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
| 2008 |
|---|
| 168 | EE | Josef Angermeier,
Ulrich Batzer,
Mateusz Majer,
Jürgen Teich,
Christopher Claus,
Walter Stechele:
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.
ARC 2008: 148-158 |
| 167 | EE | Frank Hannig,
Holger Ruckdeschel,
Hritam Dutta,
Jürgen Teich:
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.
ARC 2008: 284-289 |
| 166 | EE | Robert Brendle,
Thilo Streichert,
Dirk Koch,
Christian Haubelt,
Jürgen Teich:
Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks.
ARCS 2008: 117-129 |
| 165 | EE | Joachim Keinert,
Christian Haubelt,
Jürgen Teich:
Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication.
ARCS 2008: 130-143 |
| 164 | EE | Thilo Streichert,
Michael Glaß,
Rolf Wanka,
Christian Haubelt,
Jürgen Teich:
Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks.
ARCS 2008: 23-37 |
| 163 | EE | Martin Lukasiewycz,
Michael Glaß,
Christian Haubelt,
Jürgen Teich:
Efficient symbolic multi-objective design space exploration.
ASP-DAC 2008: 691-696 |
| 162 | EE | Daniel Ziener,
Jürgen Teich:
Concepts for Autonomous Control Flow Checking for Embedded CPUs.
ATC 2008: 234-248 |
| 161 | EE | Felix Reimann,
Michael Glabeta,
Martin Lukasiewycz,
Joachim Keinert,
Christian Haubelt,
Jürgen Teich:
Symbolic voter placement for dependability-aware system synthesis.
CODES+ISSS 2008: 237-242 |
| 160 | EE | Martin Lukasiewycz,
Michael Glaß,
Christian Haubelt,
Jürgen Teich,
Richard Regler,
Bardo Lang:
Concurrent topology and routing optimization in automotive network integration.
DAC 2008: 626-629 |
| 159 | EE | Michael Glaß,
Martin Lukasiewycz,
Felix Reimann,
Christian Haubelt,
Jürgen Teich:
Symbolic Reliability Analysis and Optimization of ECU Networks.
DATE 2008: 158-163 |
| 158 | EE | Joachim Falk,
Joachim Keinert,
Christian Haubelt,
Jürgen Teich,
Shuvra S. Bhattacharyya:
A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications.
EMSOFT 2008: 189-198 |
| 157 | EE | Dirk Koch,
Christian Haubelt,
Jürgen Teich:
Efficient Reconfigurable On-Chip Buses for FPGAs.
FCCM 2008: 287-290 |
| 156 | EE | Christophe Wolinski,
Krzysztof Kuchcinski,
Jürgen Teich,
Frank Hannig:
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.
FCCM 2008: 306-309 |
| 155 | EE | Jens Gladigau,
Christian Haubelt,
Jürgen Teich:
Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models.
FDL 2008: 1-6 |
| 154 | EE | Sándor P. Fekete,
Tom Kamphans,
Nils Schweer,
Christopher Tessars,
Jan van der Veen,
Josef Angermeier,
Dirk Koch,
Jürgen Teich:
No-break dynamic defragmentation of reconfigurable devices.
FPL 2008: 113-118 |
| 153 | EE | Dirk Koch,
Christian Beckhoff,
Jürgen Teich:
ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS.
FPL 2008: 119-124 |
| 152 | EE | Josef Angermeier,
Mateusz Majer,
Jürgen Teich,
Lars Braun,
T. Schwalb,
Philipp Graf,
Michael Hübner,
Jürgen Becker,
Enno Lübbers,
Marco Platzner,
Christopher Claus,
Walter Stechele,
Andreas Herkersdorf,
Markus Rullmann,
Renate Merker:
Fine grain reconfigurable architectures.
FPL 2008: 348 |
| 151 | EE | Sven Eisenhardt,
Thomas Schweizer,
Julio A. de Oliveira Filho,
Tobias Oppold,
Wolfgang Rosenstiel,
Alexander Thomas,
Jürgen Becker,
Frank Hannig,
Dmitrij Kissler,
Hritam Dutta,
Jürgen Teich,
Heiko Hinkelmann,
Peter Zipf,
Manfred Glesner:
Coarse-grained reconfiguration.
FPL 2008: 349 |
| 150 | EE | Christophe Wolinski,
Krzysztof Kuchcinski,
Jürgen Teich,
Frank Hannig:
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures.
FPL 2008: 391-396 |
| 149 | EE | Christopher Claus,
Walter Stechele,
Matthias Kovatsch,
Josef Angermeier,
Jürgen Teich:
A comparison of embedded reconfigurable video-processing architectures.
FPL 2008: 587-590 |
| 148 | EE | Martin Lukasiewycz,
Michael Glaß,
Christian Haubelt,
Jürgen Teich:
A feasibility-preserving local search operator for constrained discrete optimization problems.
IEEE Congress on Evolutionary Computation 2008: 1968-1975 |
| 147 | EE | Josef Angermeier,
Jürgen Teich:
Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads.
IPDPS 2008: 1-8 |
| 146 | EE | Christian Zebelein,
Joachim Falk,
Christian Haubelt,
Jürgen Teich:
Classification of General Data Flow Actors into Known Models of Computation.
MEMOCODE 2008: 119-128 |
| 145 | EE | Dmitrij Kissler,
Andreas Strawetz,
Frank Hannig,
Jürgen Teich:
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.
PATMOS 2008: 307-317 |
| 144 | EE | Martin Lukasiewycz,
Michael Glaß,
Jürgen Teich:
A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems.
PPSN 2008: 919-928 |
| 143 | EE | Stefan Wildermann,
Jürgen Teich:
3D Person Tracking with a Color-Based Particle Filter.
RobVis 2008: 327-340 |
| 142 | EE | Michael Glaß,
Martin Lukasiewycz,
Felix Reimann,
Christian Haubelt,
Jürgen Teich:
Symbolic Reliability Analysis of Self-healing Networked Embedded Systems.
SAFECOMP 2008: 139-152 |
| 141 | EE | Sándor P. Fekete,
Jan van der Veen,
Ali Ahmadinia,
Diana Göhringer,
Mateusz Majer,
Jürgen Teich:
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device.
IEEE Trans. VLSI Syst. 16(9): 1210-1219 (2008) |
| 140 | EE | Daniel Ziener,
Jürgen Teich:
Power Signature Watermarking of IP Cores for FPGAs.
Signal Processing Systems 51(1): 123-136 (2008) |
| 139 | | Jürgen Teich:
Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen).
it - Information Technology 50(5): 300-310 (2008) |
| 2007 |
|---|
| 138 | | Soonhoi Ha,
Kiyoung Choi,
Nikil D. Dutt,
Jürgen Teich:
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007
ACM 2007 |
| 137 | EE | Alexey Kupriyanov,
Frank Hannig,
Dmitrij Kissler,
Jürgen Teich,
Julien Lallet,
Olivier Sentieys,
Sébastien Pillement:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
ARCS 2007: 268-282 |
| 136 | EE | Michael Glaß,
Martin Lukasiewycz,
Thilo Streichert,
Christian Haubelt,
Jürgen Teich:
Interactive presentation: Reliability-aware system synthesis.
DATE 2007: 409-414 |
| 135 | | Jürgen Teich,
Frank Hannig,
Holger Ruckdeschel,
Hritam Dutta,
Dmitrij Kissler,
Andrej Stravet:
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.
ERSA 2007: 14-24 |
| 134 | EE | Joachim Keinert,
Joachim Falk,
Christian Haubelt,
Jürgen Teich:
Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms.
ESTImedia 2007: 113-118 |
| 133 | EE | Jens Gladigau,
Christian Haubelt,
Bernhard Niemann,
Jürgen Teich:
Mapping Actor-Oriented Models to TLM Architectures.
FDL 2007: 128-133 |
| 132 | EE | Dirk Koch,
Christian Haubelt,
Jürgen Teich:
Efficient hardware checkpointing: concepts, overhead analysis, and implementation.
FPGA 2007: 188-196 |
| 131 | EE | Joachim Keinert,
Christian Haubelt,
Jürgen Teich:
Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow.
ICSAMOS 2007: 161-168 |
| 130 | EE | Martin Lukasiewycz,
Michael Glaß,
Christian Haubelt,
Jürgen Teich:
SAT-decoding in evolutionary algorithms for discrete constrained optimization problems.
IEEE Congress on Evolutionary Computation 2007: 935-942 |
| 129 | EE | Dirk Koch,
Christian Haubelt,
Thilo Streichert,
Jürgen Teich:
Modeling and Synthesis of Hardware-Software Morphing.
ISCAS 2007: 2746-2749 |
| 128 | | Hritam Dutta,
Frank Hannig,
Alexey Kupriyanov,
Dmitrij Kissler,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach.
ReCoSoC 2007: 61-68 |
| 127 | EE | Martin Lukasiewycz,
Michael Glaß,
Christian Haubelt,
Jürgen Teich:
Solving Multi-objective Pseudo-Boolean Problems.
SAT 2007: 56-69 |
| 126 | EE | Alexey Kupriyanov,
Dmitrij Kissler,
Frank Hannig,
Jürgen Teich:
Efficient event-driven simulation of parallel processor architectures.
SCOPES 2007: 71-80 |
| 125 | EE | Thilo Streichert,
Michael Glaß,
Christian Haubelt,
Jürgen Teich:
Design space exploration of reliable networked embedded systems.
Journal of Systems Architecture 53(10): 751-763 (2007) |
| 124 | EE | Hritam Dutta,
Frank Hannig,
Holger Ruckdeschel,
Jürgen Teich:
Efficient control generation for mapping nested loop programs onto processor arrays.
Journal of Systems Architecture 53(5-6): 300-309 (2007) |
| 123 | EE | Mateusz Majer,
Jürgen Teich,
Ali Ahmadinia,
Christophe Bobda:
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer.
VLSI Signal Processing 47(1): 15-31 (2007) |
| 122 | EE | Jürgen Teich:
Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme).
it - Information Technology 49(3): 139- (2007) |
| 121 | EE | Josef Angermeier,
Diana Göhringer,
Mateusz Majer,
Jürgen Teich,
Sándor P. Fekete,
Jan van der Veen:
The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens).
it - Information Technology 49(3): 143- (2007) |
| 2006 |
|---|
| 120 | | Peter M. Athanas,
Jürgen Becker,
Gordon J. Brebner,
Jürgen Teich:
Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006
Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006 |
| 119 | EE | Hritam Dutta,
Frank Hannig,
Jürgen Teich:
Controller Synthesis for Mapping Partitioned Programs on Array Architectures.
ARCS 2006: 176-190 |
| 118 | EE | Dirk Koch,
Thilo Streichert,
Steffen Dittrich,
Christian Strengert,
Christian Haubelt,
Jürgen Teich:
An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks.
ARCS 2006: 202-216 |
| 117 | | Mateusz Majer,
Ali Ahmadinia,
Christophe Bobda,
Jürgen Teich:
A Flexible Reconfiguration Manager for the Erlangen Slot Machine.
ARCS Workshops 2006: 183-194 |
| 116 | EE | Hritam Dutta,
Frank Hannig,
Jürgen Teich,
Benno Heigl,
Heinz Hornegger:
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.
ASAP 2006: 331-340 |
| 115 | | Dmitrij Kissler,
Alexey Kupriyanov,
Frank Hannig,
Dirk Koch,
Jürgen Teich:
A Generic Framework for Rapid Prototyping of System-on-Chip Designs.
CDES 2006: 189-195 |
| 114 | EE | Jürgen Teich:
Are current ESL tools meeting the requirements of advanced embedded systems?
CODES+ISSS 2006: 166 |
| 113 | EE | Martin Streubühr,
Joachim Falk,
Christian Haubelt,
Jürgen Teich,
Rainer Dorsch,
Thomas Schlipf:
Task-accurate performance modeling in SystemC for real-time multi-processor architectures.
DATE 2006: 480-481 |
| 112 | EE | Jürgen Becker,
Jürgen Teich,
Gordon J. Brebner,
Peter M. Athanas:
06141 Abstracts Collection -- Dynamically Reconfigurable Architectures.
Dynamically Reconfigurable Architectures 2006 |
| 111 | EE | Jürgen Becker,
Jürgen Teich,
Gordon J. Brebner,
Peter M. Athanas:
06141 Executive Summary -- Dynamically Reconfigurable Architectures.
Dynamically Reconfigurable Architectures 2006 |
| 110 | EE | Diana Göhringer,
Mateusz Majer,
Jürgen Teich:
Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine.
Dynamically Reconfigurable Architectures 2006 |
| 109 | EE | Martin Lukasiewycz,
Michael Glaß,
Christian Haubelt,
Jürgen Teich:
Symbolic Archive Representation for a Fast Nondominance Test.
EMO 2006: 111-125 |
| 108 | | Dirk Koch,
Matthiaas Koerber,
Jürgen Teich:
Searching RC5-Keys with Distributed Reconfigurable Computing.
ERSA 2006: 42-48 |
| 107 | EE | Jürgen Teich,
Stefanos Kaxiras,
Toomas P. Plaks,
Krisztián Flautner:
Topic 18: Embedded Parallel Systems.
Euro-Par 2006: 1179 |
| 106 | EE | Joachim Falk,
Christian Haubelt,
Jürgen Teich:
Efficient Representation and Simulation of Model-Based Designs.
FDL 2006: 129-135 |
| 105 | EE | Daniel Ziener,
Stefan Assmus,
Jürgen Teich:
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis.
FPL 2006: 1-6 |
| 104 | EE | Sándor P. Fekete,
Jan van der Veen,
Mateusz Majer,
Jürgen Teich:
Minimizing Communication Cost for Reconfigurable Slot Modules.
FPL 2006: 1-6 |
| 103 | EE | Thilo Streichert,
Christian Haubelt,
Jürgen Teich:
Multi-Objective Topology Optimization for Networked Embedded Systems.
ICSAMOS 2006: 93-98 |
| 102 | EE | Thomas Schlichter,
Martin Lukasiewycz,
Christian Haubelt,
Jürgen Teich:
Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms.
ISVLSI 2006: 309-316 |
| 101 | EE | Hritam Dutta,
Frank Hannig,
Jürgen Teich:
Hierarchical Partitioning for Piecewise Linear Algorithms.
PARELEC 2006: 153-160 |
| 100 | | Dmitrij Kissler,
Frank Hannig,
Alexey Kupriyanov,
Jürgen Teich:
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.
ReCoSoC 2006: 31-37 |
| 99 | EE | Thilo Streichert,
Christian Strengert,
Christian Haubelt,
Jürgen Teich:
Dynamic task binding for hardware/software reconfigurable networks.
SBCCI 2006: 38-43 |
| 98 | EE | Frank Hannig,
Hritam Dutta,
Jürgen Teich:
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology.
IJES 2(1/2): 114-127 (2006) |
| 97 | EE | Sándor P. Fekete,
Ekkehard Köhler,
Jürgen Teich:
Higher-Dimensional Packing with Order Constraints.
SIAM J. Discrete Math. 20(4): 1056-1078 (2006) |
| 96 | EE | Jürgen Teich,
Shuvra S. Bhattacharyya:
Analysis of Dataflow Programs with Interval-limited Data-rates.
VLSI Signal Processing 43(2-3): 247-258 (2006) |
| 2005 |
|---|
| 95 | EE | Thomas Schlichter,
Christian Haubelt,
Frank Hannig,
Jürgen Teich:
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.
ASAP 2005: 9-14 |
| 94 | EE | Christian Haubelt,
Stephan Otto,
Cornelia Grabbe,
Jürgen Teich:
A system-level approach to hardware reconfigurable systems.
ASP-DAC 2005: 298-301 |
| 93 | EE | Thilo Streichert,
Christian Haubelt,
Jürgen Teich:
Online hardware/software partitioning in networked embedded systems.
ASP-DAC 2005: 982-985 |
| 92 | EE | S. Helwig,
Christian Haubelt,
Jürgen Teich:
Modeling and analysis of indirect communication in particle swarm optimization.
Congress on Evolutionary Computation 2005: 1246-1253 |
| 91 | EE | Thilo Streichert,
Christian Haubelt,
Jürgen Teich:
Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks.
DATE 2005: 894-895 |
| 90 | EE | Christian Haubelt,
Jürgen Gamenik,
Jürgen Teich:
Initial Population Construction for Convergence Improvement of MOEAs.
EMO 2005: 191-205 |
| 89 | | Frank Hannig,
Jürgen Teich:
Output Serialization for FPGA-based and Coarse-grained Processor Arrays.
ERSA 2005: 78-84 |
| 88 | | Jan van der Veen,
Sándor P. Fekete,
Mateusz Majer,
Ali Ahmadinia,
Christophe Bobda,
Frank Hannig,
Jürgen Teich:
Defragmenting the Module Layout of a Partially Reconfigurable Device.
ERSA 2005: 92-104 |
| 87 | EE | Christophe Bobda,
Mateusz Majer,
Ali Ahmadinia,
Thomas Haller,
André Linarth,
Jürgen Teich,
Sándor P. Fekete,
Jan van der Veen:
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.
FCCM 2005: 319-320 |
| 86 | | Christophe Bobda,
Ali Ahmadinia,
Mateusz Majer,
Jürgen Teich,
Sándor P. Fekete,
Jan van der Veen:
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.
FPL 2005: 153-158 |
| 85 | | Christophe Bobda,
Mateusz Majer,
Ali Ahmadinia,
Thomas Haller,
André Linarth,
Jürgen Teich:
The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms.
FPT 2005: 37-42 |
| 84 | EE | Thomas Schlichter,
Christian Haubelt,
Jürgen Teich:
Improving EA-based design space exploration by utilizing symbolic feasibility tests.
GECCO 2005: 1945-1952 |
| 83 | | Christian Haubelt,
Marek Jersak,
Kai Richter,
Karsten Strehl,
Dirk Ziegenbein,
Rolf Ernst,
Jürgen Teich,
Lothar Thiele:
SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme.
GI Jahrestagung (2) 2005: 693-697 |
| 82 | EE | Ali Ahmadinia,
Christophe Bobda,
Ji Ding,
Mateusz Majer,
Jürgen Teich,
Sándor P. Fekete,
Jan van der Veen:
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices.
IEEE International Workshop on Rapid System Prototyping 2005: 84-90 |
| 81 | EE | Mateusz Majer,
Christophe Bobda,
Ali Ahmadinia,
Jürgen Teich:
Packet Routing in Dynamically Changing Networks on Chip.
IPDPS 2005 |
| 80 | EE | Sanaz Mostaghim,
Jürgen Teich:
A New Approach on Many Objective Diversity Measurement.
Practical Approaches to Multi-Objective Optimization 2005 |
| 79 | | Frank Hannig,
Hritam Dutta,
Alexey Kupriyanov,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Ronan Keryell,
Bernard Pottier,
Daniel Chillet,
Daniel Menard,
Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures.
ReCoSoC 2005: 27-34 |
| 78 | EE | Holger Ruckdeschel,
Hritam Dutta,
Frank Hannig,
Jürgen Teich:
Automatic FIR Filter Generation for FPGAs.
SAMOS 2005: 51-61 |
| 77 | EE | Ali Ahmadinia,
Christophe Bobda,
Ji Ding,
Mateusz Majer,
Jürgen Teich,
Sándor P. Fekete,
Jan van der Veen:
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices
CoRR abs/cs/0503066: (2005) |
| 76 | EE | Jan van der Veen,
Sándor P. Fekete,
Ali Ahmadinia,
Christophe Bobda,
Frank Hannig,
Jürgen Teich:
Defragmenting the Module Layout of a Partially Reconfigurable Device
CoRR abs/cs/0505005: (2005) |
| 75 | EE | Christophe Bobda,
Ali Ahmadinia,
Mateusz Majer,
Jürgen Teich,
Sándor P. Fekete,
Jan van der Veen:
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices
CoRR abs/cs/0510039: (2005) |
| 74 | EE | Ali Ahmadinia,
Christophe Bobda,
Jürgen Teich:
Online placement for dynamically reconfigurable devices.
IJES 1(3/4): 165-178 (2005) |
| 2004 |
|---|
| 73 | EE | Ali Ahmadinia,
Christophe Bobda,
Jürgen Teich:
A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware.
ARCS 2004: 125-139 |
| 72 | | Christophe Bobda,
Ali Ahmadinia,
Jürgen Teich:
Generation of Distributed Arithmetic Designs for Reconfigurable Application.
ARCS Workshops 2004: 205-214 |
| 71 | EE | Frank Hannig,
Jürgen Teich:
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.
ASAP 2004: 17-27 |
| 70 | EE | Dirk Koch,
Jürgen Teich:
Platform-independent methodology for partial reconfiguration.
Conf. Computing Frontiers 2004: 398-403 |
| 69 | EE | Christophe Bobda,
Mateusz Majer,
Dirk Koch,
Ali Ahmadinia,
Jürgen Teich:
A Dynamic NoC Approach for Communication in Reconfigurable Devices.
FPL 2004: 1032-1036 |
| 68 | EE | Ali Ahmadinia,
Christophe Bobda,
Sándor P. Fekete,
Jürgen Teich,
Jan van der Veen:
Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices.
FPL 2004: 847-851 |
| 67 | EE | Neal K. Bambha,
Shuvra S. Bhattacharyya,
Jürgen Teich,
Eckart Zitzler:
Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms.
GECCO (2) 2004: 383-384 |
| 66 | EE | Ali Ahmadinia,
Christophe Bobda,
Marcus Bednara,
Jürgen Teich:
A New Approach for On-line Placement on Reconfigurable Devices.
IPDPS 2004 |
| 65 | EE | Frank Hannig,
Hritam Dutta,
Jürgen Teich:
Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology.
IPDPS 2004 |
| 64 | EE | Ali Ahmadinia,
Christophe Bobda,
Marcus Bednara,
Jürgen Teich:
Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration.
IPDPS 2004 |
| 63 | EE | Frank Hannig,
Jürgen Teich:
Dynamic Piecewise Linear/Regular Algorithms.
PARELEC 2004: 79-84 |
| 62 | EE | Christian Haubelt,
Dirk Koch,
Jürgen Teich:
Basic OS Support for Distributed Reconfigurable Hardware.
SAMOS 2004: 30-38 |
| 61 | EE | Jürgen Teich,
Shuvra S. Bhattacharyya:
Analysis of Dataflow Programs with Interval-Limited Data-Rates.
SAMOS 2004: 507-518 |
| 60 | EE | Alexey Kupriyanov,
Frank Hannig,
Jürgen Teich:
High-Speed Event-Driven RTL Compiled Simulation.
SAMOS 2004: 519-529 |
| 59 | EE | Ali Ahmadinia,
Christophe Bobda,
Dirk Koch,
Mateusz Majer,
Jürgen Teich:
Task scheduling for heterogeneous reconfigurable computers.
SBCCI 2004: 22-27 |
| 58 | EE | Ali Ahmadinia,
Christophe Bobda,
Sándor P. Fekete,
Jürgen Teich,
Jan van der Veen:
Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices
CoRR cs.DS/0406035: (2004) |
| 57 | | Neal K. Bambha,
Shuvra S. Bhattacharyya,
Jürgen Teich,
Eckart Zitzler:
Systematic integration of parameterized local search into evolutionary algorithms.
IEEE Trans. Evolutionary Computation 8(2): 137-155 (2004) |
| 2003 |
|---|
| 56 | EE | Jens Gerling,
Oliver Stübbe,
Jürgen Schrage,
Gerd Mrozynski,
Jürgen Teich:
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects.
DATE 2003: 11110-11111 |
| 55 | EE | Christian Haubelt,
Jürgen Teich,
Rainer Feldmann,
Burkhard Monien:
SAT-Based Techniques in System Synthesis.
DATE 2003: 11168-11169 |
| 54 | EE | Oliver Schütze,
Sanaz Mostaghim,
Michael Dellnitz,
Jürgen Teich:
Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques.
EMO 2003: 118-132 |
| 53 | EE | Christian Haubelt,
Sanaz Mostaghim,
Jürgen Teich,
Ambrish Tyagi:
Solving Hierarchical Optimization Problems Using MOEAs.
EMO 2003: 162-176 |
| 52 | EE | Rainer Feldmann,
Christian Haubelt,
Burkhard Monien,
Jürgen Teich:
Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques.
FPL 2003: 478-487 |
| 51 | EE | Cornelia Grabbe,
Marcus Bednara,
Joachim von zur Gathen,
Jamshid Shokrollahi,
Jürgen Teich:
A High Performance VLIW Processor for Finite Field Arithmetic.
IPDPS 2003: 189 |
| 50 | EE | Cornelia Grabbe,
Marcus Bednara,
Jürgen Teich,
Joachim von zur Gathen,
Jamshid Shokrollahi:
FPGA designs of parallel high performance GF(2233) multipliers.
ISCAS (2) 2003: 268-271 |
| 49 | EE | Christian Haubelt,
Dirk Koch,
Jürgen Teich:
ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware.
SBCCI 2003: 343-348 |
| 48 | | Ali Ahmadinia,
Jürgen Teich:
Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead.
VLSI-SOC 2003: 118-122 |
| 47 | EE | Sándor P. Fekete,
Ekkehard Köhler,
Jürgen Teich:
Higher-Dimensional Packing with Order Constraints
CoRR cs.DS/0308006: (2003) |
| 46 | EE | Dirk Fischer,
Jürgen Teich,
Ralph Weper,
Michael Thies:
BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs.
Journal of Circuits, Systems, and Computers 12(3): 353- (2003) |
| 45 | EE | Marcus Bednara,
Jürgen Teich:
Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms.
The Journal of Supercomputing 26(2): 149-165 (2003) |
| 2002 |
|---|
| 44 | | Ed F. Deprettere,
Jürgen Teich,
Stamatis Vassiliadis:
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Springer 2002 |
| 43 | EE | Dirk Fischer,
Jürgen Teich,
Michael Thies,
Ralph Weper:
Efficient architecture/compiler co-exploration for ASIPs.
CASES 2002: 27-34 |
| 42 | EE | Jürgen Teich,
Markus Köster:
(Self-)reconfigurable Finite State Machines: Theory and Implementation.
DATE 2002: 559-567 |
| 41 | EE | Christian Haubelt,
Jürgen Teich,
Kai Richter,
Rolf Ernst:
System Design for Flexibility.
DATE 2002: 854-861 |
| 40 | EE | Jürgen Teich,
Lothar Thiele:
Exact Partitioning of Affine Dependence Algorithms.
Embedded Processor Design Challenges 2002: 135-153 |
| 39 | EE | Marcus Bednara,
Frank Hannig,
Jürgen Teich:
Generation of Distributed Loop Control.
Embedded Processor Design Challenges 2002: 154-170 |
| 38 | EE | Christian Haubelt,
Jürgen Teich,
Kai Richter,
Rolf Ernst:
Flexibility/Cost-Tradeoffs of Platform-Based Systems.
Embedded Processor Design Challenges 2002: 38-56 |
| 37 | EE | Marcus Bednara,
M. Daldrup,
Joachim von zur Gathen,
Jamshid Shokrollahi,
Jürgen Teich:
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms.
IPDPS 2002 |
| 36 | EE | Marcus Bednara,
M. Daldrup,
Jürgen Teich,
Joachim von zur Gathen,
Jamshid Shokrollahi:
Tradeoff analysis of FPGA based elliptic curve cryptography.
ISCAS (5) 2002: 797-800 |
| 35 | EE | Frank Hannig,
Jürgen Teich:
Energy estimation of nested loop programs.
SPAA 2002: 149-150 |
| 34 | EE | Dirk Ziegenbein,
Kai Richter,
Rolf Ernst,
Lothar Thiele,
Jürgen Teich:
SPI - a system model for heterogeneously specified embedded systems.
IEEE Trans. VLSI Syst. 10(4): 379-389 (2002) |
| 2001 |
|---|
| 33 | EE | Dirk Fischer,
Jürgen Teich,
Ralph Weper,
Uwe Kastens,
Michael Thies:
Design space characterization for architecture/compiler co-exploration.
CASES 2001: 108-115 |
| 32 | EE | Neal K. Bambha,
Shuvra S. Bhattacharyya,
Jürgen Teich,
Eckart Zitzler:
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors.
CODES 2001: 243-248 |
| 31 | EE | Sándor P. Fekete,
Ekkehard Köhler,
Jürgen Teich:
Optimal FPGA module placement with temporal precedence constraints.
DATE 2001: 658-667 |
| 30 | EE | Jürgen Teich:
Pareto-Front Exploration with Uncertain Objectives.
EMO 2001: 314-328 |
| 29 | EE | Frank Hannig,
Jürgen Teich:
Design Space Exploration for Massively Parallel Processor Arrays.
PaCT 2001: 51-65 |
| 28 | EE | Sándor P. Fekete,
Ekkehard Köhler,
Jürgen Teich:
Higher-Dimensional Packing with Order Constraints.
WADS 2001: 300-312 |
| 27 | EE | Sándor P. Fekete,
Ekkehard Köhler,
Jürgen Teich:
Extending Partial Suborders.
Electronic Notes in Discrete Mathematics 8: 34-37 (2001) |
| 26 | EE | Karsten Strehl,
Lothar Thiele,
Matthias Gries,
Dirk Ziegenbein,
Rolf Ernst,
Jürgen Teich:
FunState-an internal design representation for codesign.
IEEE Trans. VLSI Syst. 9(4): 524-544 (2001) |
| 25 | | Jürgen Teich,
Sándor P. Fekete,
Jörg Schepers:
Optimization of Dynamic Hardware Reconfigurations.
The Journal of Supercomputing 19(1): 57-75 (2001) |
| 2000 |
|---|
| 24 | EE | Marcus Bednara,
Oliver Beyer,
Jürgen Teich,
Rolf Wanka:
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter.
ASAP 2000: 299-308 |
| 23 | EE | Jürgen Teich,
Philipp W. Kutter,
Ralph Weper:
Description and Simulation of Microprocessor Instruction Sets Using ASMs.
Abstract State Machines 2000: 266-286 |
| 22 | EE | Jürgen Teich,
Ralph Weper,
Dirk Fischer,
Stefan Trinkert:
A joined architecture/compiler design environment for ASIPs.
CASES 2000: 26-33 |
| 21 | | F. Cieslok,
H. Esau,
Jürgen Teich:
EXPLORA - Generic Design Space Exploration during Embedded System Synthesis.
DIPES 2000: 215-226 |
| 20 | EE | Eckart Zitzler,
Jürgen Teich,
S. S. Bhattclcharyya:
Evolutionary algorithms for the synthesis of embedded software.
IEEE Trans. VLSI Syst. 8(4): 452-455 (2000) |
| 19 | | Lothar Thiele,
Jürgen Teich,
Karsten Strehl:
Regular state machines.
Parallel Algorithms Appl. 15(3-4): 265-300 (2000) |
| 18 | EE | Eckart Zitzler,
Jürgen Teich,
Shuvra S. Bhattacharyya:
Multidimensional Exploration of Software Implementations for DSP Algorithms.
VLSI Signal Processing 24(1): 83-98 (2000) |
| 1999 |
|---|
| 17 | EE | Jürgen Teich,
Eckart Zitzler,
Shuvra S. Bhattacharyya:
3D exploration of software schedules for DSP algorithms.
CODES 1999: 168-172 |
| 16 | EE | Karsten Strehl,
Lothar Thiele,
Dirk Ziegenbein,
Rolf Ernst,
Jürgen Teich:
Scheduling hardware/software systems using symbolic techniques.
CODES 1999: 173-177 |
| 15 | EE | Kai Richter,
Dirk Ziegenbein,
Rolf Ernst,
Lothar Thiele,
Jürgen Teich:
Representation of Function Variants for Embedded System Optimization and Synthesis.
DAC 1999: 517-522 |
| 14 | EE | Lothar Thiele,
Karsten Strehl,
Dirk Ziegenbein,
Rolf Ernst,
Jürgen Teich:
FunState - an internal design representation for codesign.
ICCAD 1999: 558-565 |
| 13 | | Jürgen Teich,
Sándor P. Fekete,
Jörg Schepers:
Compile-time Optimization of Dynamic Hardware Reconfigurations.
PDPTA 1999: 1097-1103 |
| 1998 |
|---|
| 12 | EE | Michael Eisenring,
Jürgen Teich:
Domain-specific interface generation from dataflow specifications.
CODES 1998: 43-47 |
| 11 | EE | Dirk Ziegenbein,
Rolf Ernst,
Kai Richter,
Jürgen Teich,
Lothar Thiele:
Combining multiple models of computation for scheduling and allocation.
CODES 1998: 9-13 |
| 10 | EE | Michael Eisenring,
Jürgen Teich:
Interfacing Hardware and Software.
FPL 1998: 520-524 |
| 9 | EE | Dirk Ziegenbein,
Kai Richter,
Rolf Ernst,
Jürgen Teich,
Lothar Thiele:
Representation of process mode correlation for scheduling.
ICCAD 1998: 54-61 |
| 8 | EE | Jürgen Teich,
Eckart Zitzler,
Shuvra S. Bhattacharyya:
Buffer Memory Optimization in DSP Applications - An Evolutionary Approach.
PPSN 1998: 885-896 |
| 1997 |
|---|
| 7 | EE | Jürgen Teich,
Tobias Blickle,
Lothar Thiele:
An evolutionary approach to system-level synthesis.
CODES 1997: 167-172 |
| 6 | EE | Jürgen Teich,
Lothar Thiele,
Sundararajan Sriram,
Michael Martin:
Performance analysis and optimization of mixed asynchronous synchronous systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 473-484 (1997) |
| 5 | EE | Jürgen Teich,
Lothar Thiele,
Lee Z. Zhang:
Partitioning Processor Arrays under Resource Constraints.
VLSI Signal Processing 17(1): 5-20 (1997) |
| 1996 |
|---|
| 4 | EE | Jürgen Teich,
Lothar Thiele,
Li Zhang:
Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources.
ASAP 1996: 131-144 |
| 1995 |
|---|
| 3 | EE | Jürgen Teich,
Lothar Thiele,
Edward A. Lee:
Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model.
ISSS 1995: 156-161 |
| 2 | EE | Christian Schwarz,
Jürgen Teich,
Alek Vainshtein,
Emo Welzl,
Brian L. Evans:
Minimal Enclosing Parallelogram with Application.
Symposium on Computational Geometry 1995: C34-C35 |
| 1991 |
|---|
| 1 | EE | Jürgen Teich,
Lothar Thiele:
Control generation in the design of processor arrays.
VLSI Signal Processing 3(1-2): 77-92 (1991) |
