2009 | ||
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144 | Paul Chow, Peter Y. K. Cheung: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009 ACM 2009 | |
143 | EE | Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung: Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ARC 2009: 133-144 |
142 | EE | Tobias Becker, Wayne Luk, Peter Y. K. Cheung: Parametric Design for Reconfigurable Software-Defined Radio. ARC 2009: 15-26 |
141 | EE | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 305-315 (2009) |
140 | EE | Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung: Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. TRETS 1(4): (2009) |
2008 | ||
139 | EE | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC 2008: 124-135 |
138 | EE | Ben Cope, Peter Y. K. Cheung, Wayne Luk: Using Reconfigurable Logic to Optimise GPU Memory Accesses. DATE 2008: 44-49 |
137 | EE | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258 |
136 | EE | N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Measuring and modeling FPGA clock variability. FPGA 2008: 258 |
135 | EE | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL 2008: 179-184 |
134 | EE | Edward Stott, N. Pete Sedcole, Peter Y. K. Cheung: Fault tolerant methods for reliability in FPGAs. FPL 2008: 415-420 |
133 | EE | Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa: Towards benchmarking energy efficiency of reconfigurable architectures. FPL 2008: 691-694 |
132 | EE | Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole: Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704 |
131 | EE | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung: Video enhancement on an adaptive image sensor. ICIP 2008: 681-684 |
130 | EE | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith: Glitch-aware output switching activity from word-level statistics. ISCAS 2008: 1792-1795 |
129 | EE | N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Characterisation of FPGA Clock Variability. ISVLSI 2008: 322-328 |
128 | EE | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214 |
127 | EE | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10 |
126 | EE | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58 |
125 | EE | Peter Y. K. Cheung, Alexandre Yakovlev: Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber. Comput. J. 51(6): 741-742 (2008) |
124 | EE | Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung: Outer Loop Pipelining for Application Specific Datapaths in FPGAs. IEEE Trans. VLSI Syst. 16(10): 1268-1280 (2008) |
123 | EE | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. IEEE Trans. VLSI Syst. 16(6): 733-744 (2008) |
122 | EE | Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos: Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. Signal Processing Systems 51(1): 3-21 (2008) |
121 | EE | N. Pete Sedcole, Peter Y. K. Cheung: Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. TRETS 1(2): (2008) |
2007 | ||
120 | EE | Sutjipto Arifin, Peter Y. K. Cheung: A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information. ACM Multimedia 2007: 68-77 |
119 | EE | Ben Cope, Peter Y. K. Cheung, Wayne Luk: Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. ASAP 2007: 308-313 |
118 | EE | Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung: Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. FCCM 2007: 141-150 |
117 | EE | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Automatic On-chip Memory Minimization for Data Reuse. FCCM 2007: 251-260 |
116 | EE | Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: A Hybrid Memory Sub-system for Video Coding Applications. FCCM 2007: 317-318 |
115 | EE | Tobias Becker, Wayne Luk, Peter Y. K. Cheung: Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. FCCM 2007: 35-44 |
114 | EE | N. Pete Sedcole, Peter Y. K. Cheung: Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. FPGA 2007: 178-187 |
113 | EE | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung: On the feasibility of early routing capacitance estimation for FPGAs. FPL 2007: 234-239 |
112 | EE | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung: Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. FPL 2007: 345-350 |
111 | EE | Sutjipto Arifin, Peter Y. K. Cheung: A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information. ICIP (6) 2007: 333-336 |
110 | EE | Sutjipto Arifin, Peter Y. K. Cheung: A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory". ICSC 2007: 147-154 |
109 | EE | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam: A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182 |
108 | EE | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. VLSI Syst. 15(9): 1003-1016 (2007) |
2006 | ||
107 | EE | Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC 2006: 205-216 |
106 | EE | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley: Hardware efficient architectures for Eigenvalue computation. DATE 2006: 953-958 |
105 | EE | Sutjipto Arifin, Peter Y. K. Cheung: A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. DATE Designers' Forum 2006: 227-232 |
104 | EE | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. FCCM 2006: 275-276 |
103 | EE | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield enhancements of design-specific FPGAs. FPGA 2006: 93-100 |
102 | EE | Sutjipto Arifin, Peter Y. K. Cheung: Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. FPL 2006: 1-4 |
101 | EE | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. FPL 2006: 1-6 |
100 | EE | Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk: Efficient Realtime FPGA Implementation of the Trace Transform. FPL 2006: 1-6 |
99 | EE | Christos-Savvas Bouganis, Peter Y. K. Cheung, Li Zhaoping: FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. FPL 2006: 1-6 |
98 | EE | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL 2006: 1-6 |
97 | EE | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8 |
96 | EE | Sutjipto Arifin, Peter Y. K. Cheung: User Attention Based Arousal Content Modeling. ICIP 2006: 433-436 |
95 | EE | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung: A Spatiotemporal Saliency Framework. ICIP 2006: 437-440 |
94 | EE | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176 |
93 | EE | Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung: Fast word-level power models for synthesis of FPGA-based arithmetic. ISCAS 2006 |
2005 | ||
92 | EE | Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung: Automating custom-precision function evaluation for embedded processors. CASES 2005: 22-31 |
91 | EE | Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung: Reconfigurable Elliptic Curve Cryptosystems on a Chip. DATE 2005: 24-29 |
90 | EE | Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. DATE 2005: 8-13 |
89 | Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen: Cell Based Motion Estimators for Reconfigurable Platforms. ERSA 2005: 218-224 | |
88 | EE | Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung: A Novel 2D Filter Design Methodology for Heterogeneous Devices. FCCM 2005: 13-22 |
87 | EE | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. FPGA 2005: 138-148 |
86 | EE | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Exploration of heterogeneous reconfigurable architectures (abstract only). FPGA 2005: 268 |
85 | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Power and Area Optimization for Multiple Restricted Multiplication. FPL 2005: 112-117 | |
84 | Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. FPL 2005: 124-129 | |
83 | Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. FPL 2005: 142-147 | |
82 | Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: Heterogeneity Exploration for Multiple 2D Filter Designs. FPL 2005: 263-268 | |
81 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. FPL 2005: 341-346 | |
80 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. FPL 2005: 409-414 | |
79 | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. FPL 2005: 77-82 | |
78 | Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt: Have GPUs Made FPGAs Redundant in the Field of Video Processing? FPT 2005: 111-118 | |
77 | Laurence A. Hey, Peter Y. K. Cheung, Michael Gellman: FPGA Based Router for Cognitive Packet Networks. FPT 2005: 331-332 | |
76 | EE | Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung: A novel 2D filter design methodology. ISCAS (1) 2005: 532-535 |
75 | EE | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: A heuristic approach for multiple restricted multiplication. ISCAS (1) 2005: 692-695 |
74 | EE | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. VLSI Syst. 13(1): 39-57 (2005) |
73 | EE | Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung: Customizable elliptic curve cryptosystems. IEEE Trans. VLSI Syst. 13(9): 1048-1059 (2005) |
2004 | ||
72 | EE | Sambuddhi Hettiaratchi, Peter Y. K. Cheung: A Novel Implementation of Tile-Based Address Mapping. DATE 2004: 306-311 |
71 | Tero Rissa, Wayne Luk, Peter Y. K. Cheung: Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. ERSA 2004: 184-193 | |
70 | EE | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272 |
69 | EE | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: Migrating Functionality from ROMS to Embedded Multipliers. FCCM 2004: 287-288 |
68 | EE | Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung: Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. FCCM 2004: 79-88 |
67 | EE | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051 |
66 | EE | Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. FPL 2004: 200-208 |
65 | EE | Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko: BIST Based Interconnect Fault Location for FPGAs. FPL 2004: 322-332 |
64 | EE | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Multiple Restricted Multiplication. FPL 2004: 374-383 |
63 | EE | Christos-Savvas Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath: A Steerable Complex Wavelet Construction and Its Implementation on FPGA. FPL 2004: 394-403 |
62 | EE | Tero Rissa, Peter Y. K. Cheung, Wayne Luk: SoftSONIC: A Customisable Modular Platform for Video Applications. FPL 2004: 54-63 |
61 | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Autonomous Memory Block for reconfigurable computing. ISCAS (2) 2004: 581-584 | |
60 | EE | Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa: Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers 53(11): 1361-1362 (2004) |
59 | EE | Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: A Gaussian Noise Generator for Hardware-Based Simulations. IEEE Trans. Computers 53(12): 1523-1534 (2004) |
2003 | ||
58 | Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings Springer 2003 | |
57 | EE | Sambuddhi Hettiaratchi, Peter Y. K. Cheung: Mesh Partitioning Approach to Energy Efficient Data Layout. DATE 2003: 11076-11081 |
56 | EE | Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: A Hardware Gaussian Noise Generator for Channel Code Evaluation. FCCM 2003: 69- |
55 | EE | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. FPL 2003: 1071-1074 |
54 | EE | Andrew Royal, Peter Y. K. Cheung: Globally Asynchronous Locally Synchronous FPGA Architectures. FPL 2003: 355-364 |
53 | EE | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. FPL 2003: 396-405 |
52 | EE | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615 |
51 | EE | Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: Non-uniform Segmentation for Hardware Function Evaluation. FPL 2003: 796-807 |
50 | EE | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Architectures for function evaluation on FPGAs. ISCAS (2) 2003: 804-807 |
49 | EE | Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheung: SONICmole: a debugging environment for the UltraSONIC reconfigurable computer. ISCAS (2) 2003: 808-811 |
48 | EE | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Multitasking in hardware-software codesign for reconfigurable computer. ISCAS (5) 2003: 621-624 |
47 | EE | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. 8(3): 334-354 (2003) |
46 | EE | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Wordlength optimization for linear digital signal processing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1432-1442 (2003) |
2002 | ||
45 | EE | Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke: Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory. DATE 2002: 902-908 |
44 | EE | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum Wordlength Allocation. FCCM 2002: 219-228 |
43 | EE | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. FCCM 2002: 297-298 |
42 | EE | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. FCCM 2002: 3-12 |
41 | EE | Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi: Customising Floating-Point Designs. FCCM 2002: 315-317 |
40 | EE | Jörn Gause, Peter Y. K. Cheung, Wayne Luk: Reconfigurable Shape-Adaptive Template Matching Architectures. FCCM 2002: 98- |
39 | EE | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. FPL 2002: 1148-1151 |
38 | EE | Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang: Automating Customisation of Floating-Point Designs. FPL 2002: 523-533 |
37 | EE | Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung: Run-Time Adaptive Flexible Instruction Processors. FPL 2002: 545-555 |
36 | EE | Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke: Energy efficient address assignment through minimized memory row switching. ICCAD 2002: 577-581 |
2001 | ||
35 | EE | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Heuristic datapath allocation for multiple wordlength systems. DATE 2001: 791-797 |
34 | EE | Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk: A Digit-Serial Structure for Reconfigurable Multipliers. FPL 2001: 565-573 |
33 | EE | K. T. Tiew, A. J. Payne, Peter Y. K. Cheung: MASH delta-sigma modulators for wideband and multi-standard applications. ISCAS (4) 2001: 778-781 |
32 | EE | Nabeel Shirazi, Dan Benyamin, Wayne Luk, Peter Y. K. Cheung, Shaori Guo: Quantitative Analysis of FPGA-based Database Searching. VLSI Signal Processing 28(1-2): 85-96 (2001) |
2000 | ||
31 | EE | Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung: Flexible instruction processors. CASES 2000: 193-200 |
30 | EE | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple Precision for Resource Minimization. FCCM 2000: 307-308 |
29 | EE | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple-Wordlength Resource Binding. FPL 2000: 646-655 |
28 | EE | Jörn Gause, Peter Y. K. Cheung, Wayne Luk: Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. FPL 2000: 96-105 |
27 | Simon D. Haynes, John Stone, Peter Y. K. Cheung, Wayne Luk: Video Image Processing with the Sonic Architecture. IEEE Computer 33(4): 50-57 (2000) | |
1999 | ||
26 | EE | Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung: Reconfigurable Computing for Augmented Reality. FCCM 1999: 136-145 |
25 | EE | Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone: SONIC - A Plug-In Architecture for Video Processing. FCCM 1999: 280-281 |
24 | Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone: SONIC - A Plug-In Architecture for Video Processing. FPL 1999: 21-30 | |
23 | Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung: Quantitative Analysis of Run-Time Reconfigurable Database Search. FPL 1999: 253-263 | |
22 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. FPL 1999: 323-332 | |
1998 | ||
21 | EE | Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung: Automating Production of Run-Time Reconfigurable Designs. FCCM 1998: 147- |
20 | EE | Simon D. Haynes, Peter Y. K. Cheung: A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. FCCM 1998: 226- |
19 | EE | Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung: Run-Time Management of Dynamically Recongigurable Designs. FPL 1998: 59-68 |
1997 | ||
18 | Wayne Luk, Peter Y. K. Cheung, Manfred Glesner: Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings Springer 1997 | |
17 | EE | Pedro A. Molina, Peter Y. K. Cheung: A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. ASYNC 1997: 126-139 |
16 | EE | José T. de Sousa, Peter Y. K. Cheung: Improved diagnosis of realistic interconnect shorts. ED&TC 1997: 501-505 |
15 | EE | Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung: Compilation tools for run-time reconfigurable designs. FCCM 1997: 56-65 |
14 | Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung: Pipeline morphing and virtual pipelines. FPL 1997: 111-120 | |
13 | Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk: A reconfigurable data-localised array for morphological algorithms. FPL 1997: 344-353 | |
12 | Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford: Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. FPL 1997: 91-100 | |
11 | David S. Bormann, Peter Y. K. Cheung: Asnchronous Wrapper for Heterogeneous Systems. ICCD 1997: 307-314 | |
10 | EE | José T. de Sousa, Peter Y. K. Cheung: Diagnosis of Boards for Realistic Interconnect Shorts. J. Electronic Testing 11(2): 157-171 (1997) |
1996 | ||
9 | EE | Hasan Demirel, Thomas J. Clarke, Peter Y. K. Cheung: Adaptive Automatic Facial Feature Segmentation. FG 1996: 277-282 |
8 | EE | Timo Koskinen, Peter Y. K. Cheung: Hierarchical tolerance analysis using statistical behavioral models. IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 506-516 (1996) |
1994 | ||
7 | Salman Ahmed, Peter Y. K. Cheung, Phil Collins: A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation. EDAC-ETC-EUROASIC 1994: 665 | |
6 | Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke: Area & Time Limitations of FPGA-based Virtual Hardware. ICCD 1994: 184-189 | |
5 | Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke: Virtual Hardware and the Limits of Computational Speed-up. ISCAS 1994: 159-162 | |
4 | Salman Ahmed, Peter Y. K. Cheung: Analog Fault Diagnosis - A Practical Approach. ISCAS 1994: 351-354 | |
3 | Akachai Sang-In, Peter Y. K. Cheung: A Method of Representative Fault Selection in Digital Circuits for ATPG. ISCAS 1994: 73-76 | |
1993 | ||
2 | Nasir-ud-Din Gohar, Peter Y. K. Cheung: A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout. ISCAS 1993: 1770-1773 | |
1991 | ||
1 | Vicente Fuentes-Sánchez, Peter Y. K. Cheung: A Tag Coprocessor Architecture for Symbolic Languages. ICCD 1991: 370-373 |